1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_HW_SHARED_H__ 27 #define __DAL_HW_SHARED_H__ 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "dc_hw_types.h" 32 33 /****************************************************************************** 34 * Data types shared between different Virtual HW blocks 35 ******************************************************************************/ 36 37 #define MAX_AUDIOS 7 38 #define MAX_PIPES 6 39 #define MAX_DWB_PIPES 1 40 41 struct gamma_curve { 42 uint32_t offset; 43 uint32_t segments_num; 44 }; 45 46 struct curve_points { 47 struct fixed31_32 x; 48 struct fixed31_32 y; 49 struct fixed31_32 offset; 50 struct fixed31_32 slope; 51 52 uint32_t custom_float_x; 53 uint32_t custom_float_y; 54 uint32_t custom_float_offset; 55 uint32_t custom_float_slope; 56 }; 57 58 struct curve_points3 { 59 struct curve_points red; 60 struct curve_points green; 61 struct curve_points blue; 62 }; 63 64 struct pwl_result_data { 65 struct fixed31_32 red; 66 struct fixed31_32 green; 67 struct fixed31_32 blue; 68 69 struct fixed31_32 delta_red; 70 struct fixed31_32 delta_green; 71 struct fixed31_32 delta_blue; 72 73 uint32_t red_reg; 74 uint32_t green_reg; 75 uint32_t blue_reg; 76 77 uint32_t delta_red_reg; 78 uint32_t delta_green_reg; 79 uint32_t delta_blue_reg; 80 }; 81 82 struct dc_rgb { 83 uint32_t red; 84 uint32_t green; 85 uint32_t blue; 86 }; 87 88 struct tetrahedral_17x17x17 { 89 struct dc_rgb lut0[1229]; 90 struct dc_rgb lut1[1228]; 91 struct dc_rgb lut2[1228]; 92 struct dc_rgb lut3[1228]; 93 }; 94 struct tetrahedral_9x9x9 { 95 struct dc_rgb lut0[183]; 96 struct dc_rgb lut1[182]; 97 struct dc_rgb lut2[182]; 98 struct dc_rgb lut3[182]; 99 }; 100 101 struct tetrahedral_params { 102 union { 103 struct tetrahedral_17x17x17 tetrahedral_17; 104 struct tetrahedral_9x9x9 tetrahedral_9; 105 }; 106 bool use_tetrahedral_9; 107 bool use_12bits; 108 109 }; 110 111 /* arr_curve_points - regamma regions/segments specification 112 * arr_points - beginning and end point specified separately (only one on DCE) 113 * corner_points - beginning and end point for all 3 colors (DCN) 114 * rgb_resulted - final curve 115 */ 116 struct pwl_params { 117 struct gamma_curve arr_curve_points[34]; 118 union { 119 struct curve_points arr_points[2]; 120 struct curve_points3 corner_points[2]; 121 }; 122 struct pwl_result_data rgb_resulted[256 + 3]; 123 uint32_t hw_points_num; 124 }; 125 126 /* move to dpp 127 * while we are moving functionality out of opp to dpp to align 128 * HW programming to HW IP, we define these struct in hw_shared 129 * so we can still compile while refactoring 130 */ 131 132 enum lb_pixel_depth { 133 /* do not change the values because it is used as bit vector */ 134 LB_PIXEL_DEPTH_18BPP = 1, 135 LB_PIXEL_DEPTH_24BPP = 2, 136 LB_PIXEL_DEPTH_30BPP = 4, 137 LB_PIXEL_DEPTH_36BPP = 8 138 }; 139 140 enum graphics_csc_adjust_type { 141 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, 142 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ 143 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ 144 }; 145 146 enum ipp_degamma_mode { 147 IPP_DEGAMMA_MODE_BYPASS, 148 IPP_DEGAMMA_MODE_HW_sRGB, 149 IPP_DEGAMMA_MODE_HW_xvYCC, 150 IPP_DEGAMMA_MODE_USER_PWL 151 }; 152 153 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 154 enum gamcor_mode { 155 GAMCOR_MODE_BYPASS, 156 GAMCOR_MODE_RESERVED_1, 157 GAMCOR_MODE_USER_PWL, 158 GAMCOR_MODE_RESERVED_3 159 }; 160 #endif 161 162 enum ipp_output_format { 163 IPP_OUTPUT_FORMAT_12_BIT_FIX, 164 IPP_OUTPUT_FORMAT_16_BIT_BYPASS, 165 IPP_OUTPUT_FORMAT_FLOAT 166 }; 167 168 enum expansion_mode { 169 EXPANSION_MODE_DYNAMIC, 170 EXPANSION_MODE_ZERO 171 }; 172 173 struct default_adjustment { 174 enum lb_pixel_depth lb_color_depth; 175 enum dc_color_space out_color_space; 176 enum dc_color_space in_color_space; 177 enum dc_color_depth color_depth; 178 enum pixel_format surface_pixel_format; 179 enum graphics_csc_adjust_type csc_adjust_type; 180 bool force_hw_default; 181 }; 182 183 184 struct out_csc_color_matrix { 185 enum dc_color_space color_space; 186 uint16_t regval[12]; 187 }; 188 189 enum gamut_remap_select { 190 GAMUT_REMAP_BYPASS = 0, 191 GAMUT_REMAP_COEFF, 192 GAMUT_REMAP_COMA_COEFF, 193 GAMUT_REMAP_COMB_COEFF 194 }; 195 196 enum opp_regamma { 197 OPP_REGAMMA_BYPASS = 0, 198 OPP_REGAMMA_SRGB, 199 OPP_REGAMMA_XVYCC, 200 OPP_REGAMMA_USER 201 }; 202 203 enum optc_dsc_mode { 204 OPTC_DSC_DISABLED = 0, 205 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */ 206 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */ 207 }; 208 209 struct dc_bias_and_scale { 210 uint16_t scale_red; 211 uint16_t bias_red; 212 uint16_t scale_green; 213 uint16_t bias_green; 214 uint16_t scale_blue; 215 uint16_t bias_blue; 216 }; 217 218 enum test_pattern_dyn_range { 219 TEST_PATTERN_DYN_RANGE_VESA = 0, 220 TEST_PATTERN_DYN_RANGE_CEA 221 }; 222 223 enum test_pattern_mode { 224 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, 225 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, 226 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, 227 TEST_PATTERN_MODE_VERTICALBARS, 228 TEST_PATTERN_MODE_HORIZONTALBARS, 229 TEST_PATTERN_MODE_SINGLERAMP_RGB, 230 TEST_PATTERN_MODE_DUALRAMP_RGB, 231 TEST_PATTERN_MODE_XR_BIAS_RGB 232 }; 233 234 enum test_pattern_color_format { 235 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, 236 TEST_PATTERN_COLOR_FORMAT_BPC_8, 237 TEST_PATTERN_COLOR_FORMAT_BPC_10, 238 TEST_PATTERN_COLOR_FORMAT_BPC_12 239 }; 240 241 enum controller_dp_test_pattern { 242 CONTROLLER_DP_TEST_PATTERN_D102 = 0, 243 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, 244 CONTROLLER_DP_TEST_PATTERN_PRBS7, 245 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, 246 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, 247 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, 248 CONTROLLER_DP_TEST_PATTERN_COLORRAMP, 249 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 250 CONTROLLER_DP_TEST_PATTERN_RESERVED_8, 251 CONTROLLER_DP_TEST_PATTERN_RESERVED_9, 252 CONTROLLER_DP_TEST_PATTERN_RESERVED_A, 253 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA, 254 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR 255 }; 256 257 enum controller_dp_color_space { 258 CONTROLLER_DP_COLOR_SPACE_RGB, 259 CONTROLLER_DP_COLOR_SPACE_YCBCR601, 260 CONTROLLER_DP_COLOR_SPACE_YCBCR709, 261 CONTROLLER_DP_COLOR_SPACE_UDEFINED 262 }; 263 264 enum dc_lut_mode { 265 LUT_BYPASS, 266 LUT_RAM_A, 267 LUT_RAM_B 268 }; 269 #endif /* __DAL_HW_SHARED_H__ */ 270