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Searched refs:HDMI_ACR_CTS_44 (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.h183 SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
263 SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
459 uint8_t HDMI_ACR_CTS_44; member
590 uint32_t HDMI_ACR_CTS_44; member
Ddce_stream_encoder.c1406 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); in dce110_se_setup_hdmi_audio()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.h241 SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
445 type HDMI_ACR_CTS_44;\
Ddcn10_stream_encoder.c1337 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); in enc1_se_setup_hdmi_audio()
/drivers/gpu/drm/radeon/
Devergreen_hdmi.c90 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); in evergreen_hdmi_update_acr()
Drv770d.h792 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) macro
Devergreend.h646 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) macro
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_stream_encoder.h152 SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
Ddcn30_dio_stream_encoder.c753 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); in enc3_se_setup_hdmi_audio()
/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1431 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v6_0_audio_set_acr()
Ddce_v10_0.c1500 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v10_0_afmt_update_ACR()
Ddce_v11_0.c1542 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v11_0_afmt_update_ACR()