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Searched refs:HDMI_WP_PWR_CTRL (Results 1 – 4 of 4) sorted by relevance

/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_wp.c32 DUMPREG(HDMI_WP_PWR_CTRL); in hdmi_wp_dump()
71 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) in hdmi_wp_set_phy_pwr()
75 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
78 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) in hdmi_wp_set_phy_pwr()
91 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); in hdmi_wp_set_pll_pwr()
94 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) in hdmi_wp_set_pll_pwr()
Dhdmi.h29 #define HDMI_WP_PWR_CTRL 0x40 macro
/drivers/gpu/drm/omapdrm/dss/
Dhdmi_wp.c31 DUMPREG(HDMI_WP_PWR_CTRL); in hdmi_wp_dump()
70 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) in hdmi_wp_set_phy_pwr()
74 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr()
77 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) in hdmi_wp_set_phy_pwr()
90 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); in hdmi_wp_set_pll_pwr()
93 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) in hdmi_wp_set_pll_pwr()
Dhdmi.h33 #define HDMI_WP_PWR_CTRL 0x40 macro