1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * aQuantia Corporation Network Driver 4 * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved 5 */ 6 7 /* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific 8 * constants. 9 */ 10 11 #ifndef HW_ATL_B0_INTERNAL_H 12 #define HW_ATL_B0_INTERNAL_H 13 14 #include "../aq_common.h" 15 16 #define HW_ATL_B0_MTU_JUMBO 16352U 17 #define HW_ATL_B0_MTU 1514U 18 19 #define HW_ATL_B0_TX_RINGS 4U 20 #define HW_ATL_B0_RX_RINGS 4U 21 22 #define HW_ATL_B0_RINGS_MAX 32U 23 #define HW_ATL_B0_TXD_SIZE (16U) 24 #define HW_ATL_B0_RXD_SIZE (16U) 25 26 #define HW_ATL_B0_MAC 0U 27 #define HW_ATL_B0_MAC_MIN 1U 28 #define HW_ATL_B0_MAC_MAX 33U 29 30 /* UCAST/MCAST filters */ 31 #define HW_ATL_B0_UCAST_FILTERS_MAX 38 32 #define HW_ATL_B0_MCAST_FILTERS_MAX 8 33 34 /* interrupts */ 35 #define HW_ATL_B0_ERR_INT 8U 36 #define HW_ATL_B0_INT_MASK (0xFFFFFFFFU) 37 38 #define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000) 39 #define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000) 40 #define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000) 41 42 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001) 43 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002) 44 #define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0) 45 #define HW_ATL_B0_TXD_CTL_DD (0x00100000) 46 #define HW_ATL_B0_TXD_CTL_EOP (0x00200000) 47 48 #define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000) 49 50 #define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22) 51 #define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23) 52 #define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24) 53 #define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25) 54 #define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26) 55 #define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27) 56 #define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28) 57 58 #define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21) 59 #define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22) 60 61 #define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U 62 #define HW_ATL_B0_MPI_STATE_ADR 0x036CU 63 64 #define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU 65 #define HW_ATL_B0_MPI_SPEED_SHIFT 16U 66 67 #define HW_ATL_B0_TXBUF_MAX 160U 68 #define HW_ATL_B0_PTP_TXBUF_SIZE 8U 69 70 #define HW_ATL_B0_RXBUF_MAX 320U 71 #define HW_ATL_B0_PTP_RXBUF_SIZE 16U 72 73 #define HW_ATL_B0_RSS_REDIRECTION_MAX 64U 74 #define HW_ATL_B0_RSS_REDIRECTION_BITS 3U 75 #define HW_ATL_B0_RSS_HASHKEY_BITS 320U 76 77 #define HW_ATL_B0_TCRSS_4_8 1 78 #define HW_ATL_B0_TC_MAX 8U 79 #define HW_ATL_B0_RSS_MAX 8U 80 81 #define HW_ATL_B0_LRO_RXD_MAX 16U 82 #define HW_ATL_B0_RS_SLIP_ENABLED 0U 83 84 /* (256k -1(max pay_len) - 54(header)) */ 85 #define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U 86 87 /* (256k -1(max pay_len) - 74(header)) */ 88 #define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U 89 90 #define HW_ATL_B0_CHIP_REVISION_B0 0xA0U 91 #define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU 92 93 #define HW_ATL_B0_FW_SEMA_RAM 0x2U 94 95 #define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00) 96 #define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000) 97 98 #define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007) 99 #define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008) 100 #define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0) 101 #define HW_ATL_B0_TXC_CTL_CMD (0x00F00000) 102 #define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000) 103 104 #define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */ 105 #define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */ 106 #define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00) 107 #define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000) 108 109 #define HW_ATL_B0_RXD_DD (0x1) 110 #define HW_ATL_B0_RXD_NCEA0 (0x1) 111 112 #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F) 113 #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE_SHIFT (0x0) 114 #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0) 115 #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE_SHIFT (0x4) 116 #define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000) 117 #define HW_ATL_B0_RXD_WB_STAT_RXCTRL_SHIFT (0x13) 118 #define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000) 119 #define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000) 120 #define HW_ATL_B0_RXD_WB_STAT_HDRLEN_SHIFT (0x16) 121 122 #define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN BIT(5) 123 #define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN_DOUBLE BIT(6) 124 125 #define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001) 126 #define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002) 127 #define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C) 128 #define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004) 129 #define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008) 130 #define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010) 131 #define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0) 132 #define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000) 133 134 #define L2_FILTER_ACTION_DISCARD (0x0) 135 #define L2_FILTER_ACTION_HOST (0x1) 136 137 #define HW_ATL_B0_UCP_0X370_REG (0x370) 138 139 #define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10) 140 141 #define HW_ATL_B0_FW_VER_EXPECTED 0x01050006U 142 143 #define HW_ATL_INTR_MODER_MAX 0x1FF 144 #define HW_ATL_INTR_MODER_MIN 0xFF 145 146 #define HW_ATL_B0_MIN_RXD \ 147 (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE)) 148 #define HW_ATL_B0_MIN_TXD \ 149 (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE)) 150 151 #define HW_ATL_B0_MAX_RXD 8184U 152 #define HW_ATL_B0_MAX_TXD 8184U 153 154 #define HW_ATL_RSS_DISABLED 0x00000000U 155 #define HW_ATL_RSS_ENABLED_8TCS_2INDEX_BITS 0xA2222222U 156 #define HW_ATL_RSS_ENABLED_4TCS_3INDEX_BITS 0x80003333U 157 158 /* HW layer capabilities */ 159 160 #endif /* HW_ATL_B0_INTERNAL_H */ 161