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Searched refs:INTR_EN (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hwio.h14 #define INTR_EN 0x010 macro
Ddpu_hw_interrupts.c198 MDP_SSPP_TOP0_OFF+INTR_EN,
/drivers/mtd/nand/raw/
Ddenali.h209 #define INTR_EN(bank) (0x420 + (bank) * 0x50) macro
Ddenali.c94 iowrite32(U32_MAX, denali->reg + INTR_EN(i)); in denali_enable_irq()
103 iowrite32(0, denali->reg + INTR_EN(i)); in denali_disable_irq()
/drivers/staging/qlge/
Dqlge_dbg.c407 ql_write32(qdev, INTR_EN, in ql_get_intr_states()
409 *buf = ql_read32(qdev, INTR_EN); in ql_get_intr_states()
1335 ql_write32(qdev, INTR_EN, qdev->intr_context[i].intr_read_mask); in ql_dump_intr_states()
1336 value = ql_read32(qdev, INTR_EN); in ql_dump_intr_states()
1456 DUMP_REG(qdev, INTR_EN); in ql_dump_regs()
Dqlge_main.c593 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI); in ql_enable_interrupts()
598 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16)); in ql_disable_interrupts()
605 ql_write32(qdev, INTR_EN, ctx->intr_en_mask); in ql_enable_completion_interrupt()
612 ql_write32(qdev, INTR_EN, ctx->intr_dis_mask); in ql_disable_completion_interrupt()
Dqlge.h818 INTR_EN = 0x34, enumerator
/drivers/tty/
Drocket_int.h238 #define INTR_EN 0x08 /* allow interrupts to host */ macro