1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
4 * Ingenic XBurst platform IRQ support
5 */
6
7 #include <linux/errno.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/ioport.h>
12 #include <linux/irqchip.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/timex.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18
19 #include <asm/io.h>
20
21 struct ingenic_intc_data {
22 void __iomem *base;
23 struct irq_domain *domain;
24 unsigned num_chips;
25 };
26
27 #define JZ_REG_INTC_STATUS 0x00
28 #define JZ_REG_INTC_MASK 0x04
29 #define JZ_REG_INTC_SET_MASK 0x08
30 #define JZ_REG_INTC_CLEAR_MASK 0x0c
31 #define JZ_REG_INTC_PENDING 0x10
32 #define CHIP_SIZE 0x20
33
intc_cascade(int irq,void * data)34 static irqreturn_t intc_cascade(int irq, void *data)
35 {
36 struct ingenic_intc_data *intc = irq_get_handler_data(irq);
37 struct irq_domain *domain = intc->domain;
38 struct irq_chip_generic *gc;
39 uint32_t pending;
40 unsigned i;
41
42 for (i = 0; i < intc->num_chips; i++) {
43 gc = irq_get_domain_generic_chip(domain, i * 32);
44
45 pending = irq_reg_readl(gc, JZ_REG_INTC_PENDING);
46 if (!pending)
47 continue;
48
49 while (pending) {
50 int bit = __fls(pending);
51
52 irq = irq_linear_revmap(domain, bit + (i * 32));
53 generic_handle_irq(irq);
54 pending &= ~BIT(bit);
55 }
56 }
57
58 return IRQ_HANDLED;
59 }
60
ingenic_intc_of_init(struct device_node * node,unsigned num_chips)61 static int __init ingenic_intc_of_init(struct device_node *node,
62 unsigned num_chips)
63 {
64 struct ingenic_intc_data *intc;
65 struct irq_chip_generic *gc;
66 struct irq_chip_type *ct;
67 struct irq_domain *domain;
68 int parent_irq, err = 0;
69 unsigned i;
70
71 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
72 if (!intc) {
73 err = -ENOMEM;
74 goto out_err;
75 }
76
77 parent_irq = irq_of_parse_and_map(node, 0);
78 if (!parent_irq) {
79 err = -EINVAL;
80 goto out_free;
81 }
82
83 err = irq_set_handler_data(parent_irq, intc);
84 if (err)
85 goto out_unmap_irq;
86
87 intc->num_chips = num_chips;
88 intc->base = of_iomap(node, 0);
89 if (!intc->base) {
90 err = -ENODEV;
91 goto out_unmap_irq;
92 }
93
94 domain = irq_domain_add_linear(node, num_chips * 32,
95 &irq_generic_chip_ops, NULL);
96 if (!domain) {
97 err = -ENOMEM;
98 goto out_unmap_base;
99 }
100
101 intc->domain = domain;
102
103 err = irq_alloc_domain_generic_chips(domain, 32, 1, "INTC",
104 handle_level_irq, 0,
105 IRQ_NOPROBE | IRQ_LEVEL, 0);
106 if (err)
107 goto out_domain_remove;
108
109 for (i = 0; i < num_chips; i++) {
110 gc = irq_get_domain_generic_chip(domain, i * 32);
111
112 gc->wake_enabled = IRQ_MSK(32);
113 gc->reg_base = intc->base + (i * CHIP_SIZE);
114
115 ct = gc->chip_types;
116 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
117 ct->regs.disable = JZ_REG_INTC_SET_MASK;
118 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
119 ct->chip.irq_mask = irq_gc_mask_disable_reg;
120 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
121 ct->chip.irq_set_wake = irq_gc_set_wake;
122 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
123
124 /* Mask all irqs */
125 irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
126 }
127
128 if (request_irq(parent_irq, intc_cascade, IRQF_NO_SUSPEND,
129 "SoC intc cascade interrupt", NULL))
130 pr_err("Failed to register SoC intc cascade interrupt\n");
131 return 0;
132
133 out_domain_remove:
134 irq_domain_remove(domain);
135 out_unmap_base:
136 iounmap(intc->base);
137 out_unmap_irq:
138 irq_dispose_mapping(parent_irq);
139 out_free:
140 kfree(intc);
141 out_err:
142 return err;
143 }
144
intc_1chip_of_init(struct device_node * node,struct device_node * parent)145 static int __init intc_1chip_of_init(struct device_node *node,
146 struct device_node *parent)
147 {
148 return ingenic_intc_of_init(node, 1);
149 }
150 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init);
151 IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init);
152
intc_2chip_of_init(struct device_node * node,struct device_node * parent)153 static int __init intc_2chip_of_init(struct device_node *node,
154 struct device_node *parent)
155 {
156 return ingenic_intc_of_init(node, 2);
157 }
158 IRQCHIP_DECLARE(jz4760_intc, "ingenic,jz4760-intc", intc_2chip_of_init);
159 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
160 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
161 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
162