| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv40.c | 64 int M1 = (coef & 0x000000ff) >> 0; in read_pll_2() local
68 if ((ctrl & 0x80000000) && M1) { in read_pll_2()
69 khz = ref * N1 / M1; in read_pll_2()
125 int *N1, int *M1, int *N2, int *M2, int *log2P) in nv40_clk_calc_pll() argument
138 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P); in nv40_clk_calc_pll()
151 int N1, M1, N2, M2, log2P; in nv40_clk_calc() local
156 &N1, &M1, &N2, &M2, &log2P); in nv40_clk_calc()
162 clk->npll_coef = (N1 << 8) | M1; in nv40_clk_calc()
165 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_clk_calc()
171 &N1, &M1, NULL, NULL, &log2P); in nv40_clk_calc()
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| D | pllnv04.c | 151 int M1, N1, M2, N2, log2P; in getMNP_double() local
164 for (M1 = minM1; M1 <= maxM1; M1++) { in getMNP_double()
165 if (crystal/M1 < minU1) in getMNP_double()
167 if (crystal/M1 > maxU1) in getMNP_double()
171 calcclk1 = crystal * N1 / M1; in getMNP_double()
212 *pM1 = M1; in getMNP_double()
228 int *N1, int *M1, int *N2, int *M2, int *P) in nv04_pll_calc() argument
233 ret = getMNP_single(subdev, info, freq, N1, M1, P); in nv04_pll_calc()
239 ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P); in nv04_pll_calc()
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| D | nv04.c | 35 int N1, M1, N2, M2, P; in nv04_clk_pll_calc() local
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P); in nv04_clk_pll_calc()
40 pv->M1 = M1; in nv04_clk_pll_calc()
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| D | mcp77.c | 57 int N1, M1; in read_pll() local
71 M1 = (coef & 0x000000ff); in read_pll()
72 if ((ctrl & 0x80000000) && M1) { in read_pll()
73 clock = ref * N1 / M1; in read_pll()
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| D | nv50.c | 166 int N1, N2, M1, M2; in read_pll() local
177 M1 = (coef & 0x000000ff); in read_pll()
178 if ((ctrl & 0x80000000) && M1) { in read_pll()
179 freq = ref * N1 / M1; in read_pll()
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| D | pll.h | 9 int *N1, int *M1, int *N2, int *M2, int *P);
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| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv50.c | 41 int N1, M1, N2, M2, P; in nv50_devinit_pll_set() local
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv50_devinit_pll_set()
60 nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1); in nv50_devinit_pll_set()
69 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
73 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
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| D | nv04.c | 164 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) in setPLL_single()
363 int N1, M1, N2, M2, P; in nv04_devinit_pll_set() local
370 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv04_devinit_pll_set()
376 pv.M1 = M1; in nv04_devinit_pll_set()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv40.c | 40 int N1, M1, N2, M2; in nv40_ram_calc() local
49 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P); in nv40_ram_calc()
57 ram->coef = (N1 << 8) | M1; in nv40_ram_calc()
60 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_ram_calc()
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| D | ramgf100.c | 143 int N1, M1, P; in gf100_ram_calc() local
216 &N1, NULL, &M1, &P); in gf100_ram_calc()
225 ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1); in gf100_ram_calc()
231 &N1, NULL, &M1, &P); in gf100_ram_calc()
238 ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1); in gf100_ram_calc()
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| D | ramgk104.c | 133 int N1, fN1, M1, P1; member
161 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); in r1373f4_init()
703 const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); in gk104_ram_calc_sddr3()
989 int *N1, int *fN1, int *M1, int *P1, in gk104_pll_calc_hiclk() argument
995 *M1 = 1; in gk104_pll_calc_hiclk()
1033 *fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal); in gk104_pll_calc_hiclk()
1066 &ram->N1, &ram->fN1, &ram->M1, &ram->P1, in gk104_ram_calc_xits()
1078 &ram->fN1, &ram->M1, &ram->P1); in gk104_ram_calc_xits()
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| D | ramnv50.c | 231 int N1, M1, N2, M2, P; in nv50_ram_calc() local
332 &N1, &M1, &N2, &M2, &P); in nv50_ram_calc()
356 ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); in nv50_ram_calc()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| D | pll.h | 9 uint8_t N1, M1, N2, M2; member
11 uint8_t M1, N1, M2, N2;
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.c | 153 pllvals->M1 &= 0xf; /* only 4 bits */ in nouveau_hw_decode_pll()
208 if (!pv->M1 || !pv->M2) in nouveau_hw_pllvals_to_clk()
211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; in nouveau_hw_pllvals_to_clk()
271 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && in nouveau_hw_fix_bad_vpll()
279 pv.M1 = pll_lim.vco1.max_m; in nouveau_hw_fix_bad_vpll()
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| D | crtc.c | 166 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); in nv_crtc_calc_state_ext()
169 pv->N1, pv->M1, pv->log2P); in nv_crtc_calc_state_ext()
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| /drivers/net/wireless/realtek/rtl818x/ |
| D | Kconfig | 45 Dlink DWL-650 v M1
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| /drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g4.c | 1519 #define M1 185 macro
1520 SIG_EXPR_LIST_DECL_SINGLE(M1, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
1521 SIG_EXPR_LIST_DECL_SINGLE(M1, ADC9, ADC9);
1522 PIN_DECL_(M1, SIG_EXPR_LIST_PTR(M1, GPIOX1), SIG_EXPR_LIST_PTR(M1, ADC9));
1523 FUNC_GROUP_DECL(ADC9, M1);
2057 ASPEED_PINCTRL_PIN(M1),
2510 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13),
2511 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13),
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| /drivers/eisa/ |
| D | eisa.ids | 28 ACR1341 "M1 486SX/20 CPU Board"
29 ACR1351 "M1 486SX/20 CPU Board"
30 ACR1361 "M1 487/20 CPU Board"
31 ACR1371 "M1 487/20 CPU Board"
32 ACR1381 "M1 486/20 CPU Board"
33 ACR1391 "M1 486/20 CPU Board"
34 ACR1581 "M1 486/33 CPU Board"
35 ACR1591 "M1 486/33 CPU Board"
36 ACR15A1 "M1 486/33 CPU Board"
37 ACR15B1 "M1 486/33 CPU Board"
[all …]
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| /drivers/staging/comedi/ |
| D | Kconfig | 261 Enable support for Measurement Computing CIO-DAS16/M1 ISA cards.
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