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Searched refs:MHZ (Results 1 – 25 of 48) sorted by relevance

12

/drivers/clk/samsung/
Dclk-s3c2410.c123 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
124 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
125 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
126 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
127 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
129 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
130 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
131 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
132 PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
133 PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
[all …]
Dclk-exynos3250.c670 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
671 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
672 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
673 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
674 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
675 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
676 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
677 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
678 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
679 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
[all …]
Dclk-exynos4.c1071 PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
1072 PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
1073 PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
1074 PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
1075 PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
1076 PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
1077 PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
1078 PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
1079 PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
1084 PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
[all …]
Dclk-exynos5420.c1400 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1401 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1402 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1403 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1404 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1405 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1406 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1407 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1408 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1409 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
[all …]
Dclk-exynos5250.c691 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
693 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
700 PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
701 PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
702 PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
703 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
704 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
705 PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
706 PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
707 PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
[all …]
Dclk-exynos5260.c23 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
24 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
25 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
26 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
27 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
28 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
29 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
30 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
31 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
32 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
[all …]
Dclk-exynos5410.c227 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
228 PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
229 PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
230 PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
231 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
232 PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
233 PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
234 PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
235 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
236 PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
[all …]
Dclk-exynos5433.c715 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
716 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
717 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
718 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
719 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
720 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
721 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
722 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
723 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
724 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
[all …]
/drivers/clk/
Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/drivers/net/can/softing/
Dsofting_cs.c26 #define MHZ (1000*1000) macro
33 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
45 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
57 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
69 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
81 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
93 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
105 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
117 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
129 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
/drivers/soc/xilinx/
Dxlnx_vcu.c88 #define MHZ 1000000 macro
89 #define FVCO_MIN (1500U * MHZ)
90 #define FVCO_MAX (3000U * MHZ)
94 #define LIMIT (10 * MHZ)
305 coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ; in xvcu_set_vcu_pll_info()
306 mcuclk = xvcu_read(xvcu->logicore_reg_ba, VCU_MCU_CLK) * MHZ; in xvcu_set_vcu_pll_info()
312 refclk = (inte * MHZ) + (deci * (MHZ / FRAC)); in xvcu_set_vcu_pll_info()
/drivers/clk/sirf/
Dclk-common.c12 #define MHZ (KHZ * KHZ) macro
90 WARN_ON(fin % MHZ); in pll_clk_recalc_rate()
91 return fin / MHZ * nf / nr / od * MHZ; in pll_clk_recalc_rate()
105 rate = rate - rate % MHZ; in pll_clk_round_rate()
107 nf = rate / MHZ; in pll_clk_round_rate()
115 nr = fin / MHZ; in pll_clk_round_rate()
137 nf = rate / MHZ; in pll_clk_set_rate()
138 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) in pll_clk_set_rate()
142 BUG_ON(fin < MHZ); in pll_clk_set_rate()
144 nr = fin / MHZ; in pll_clk_set_rate()
[all …]
/drivers/clk/mediatek/
Dclk-mt2701.c30 108 * MHZ),
32 400 * MHZ),
36 340 * MHZ),
38 340 * MHZ),
40 340 * MHZ),
42 27 * MHZ),
44 416 * MHZ),
46 143 * MHZ),
48 27 * MHZ),
923 #define MT8590_PLL_FMAX (2000 * MHZ)
Dclk-mt8183.c1064 #define MT8183_PLL_FMAX (3800UL * MHZ)
1065 #define MT8183_PLL_FMIN (1500UL * MHZ)
1107 { .div = 1, .freq = 1500 * MHZ },
1108 { .div = 2, .freq = 750 * MHZ },
1109 { .div = 3, .freq = 375 * MHZ },
1116 { .div = 1, .freq = 1600 * MHZ },
1117 { .div = 2, .freq = 800 * MHZ },
1118 { .div = 3, .freq = 400 * MHZ },
1119 { .div = 4, .freq = 200 * MHZ },
/drivers/gpu/drm/exynos/
Dexynos_drm_dsi.c539 #ifndef MHZ
540 #define MHZ (1000*1000) macro
554 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); in exynos_dsi_pll_find_pms()
555 p_max = fin / (6 * MHZ); in exynos_dsi_pll_find_pms()
570 if (tmp < 500 * MHZ || in exynos_dsi_pll_find_pms()
571 tmp > driver_data->max_freq * MHZ) in exynos_dsi_pll_find_pms()
623 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, in exynos_dsi_set_pll()
624 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, in exynos_dsi_set_pll()
625 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, in exynos_dsi_set_pll()
626 770 * MHZ, 870 * MHZ, 950 * MHZ, in exynos_dsi_set_pll()
[all …]
/drivers/phy/samsung/
Dphy-exynos4x12-usb2.c140 case 10 * MHZ: in exynos4x12_rate_to_clk()
143 case 12 * MHZ: in exynos4x12_rate_to_clk()
149 case 20 * MHZ: in exynos4x12_rate_to_clk()
152 case 24 * MHZ: in exynos4x12_rate_to_clk()
155 case 50 * MHZ: in exynos4x12_rate_to_clk()
Dphy-exynos5250-usb2.c150 case 10 * MHZ: in exynos5250_rate_to_clk()
153 case 12 * MHZ: in exynos5250_rate_to_clk()
159 case 20 * MHZ: in exynos5250_rate_to_clk()
162 case 24 * MHZ: in exynos5250_rate_to_clk()
165 case 50 * MHZ: in exynos5250_rate_to_clk()
Dphy-s5pv210-usb2.c73 case 12 * MHZ: in s5pv210_rate_to_clk()
76 case 24 * MHZ: in s5pv210_rate_to_clk()
79 case 48 * MHZ: in s5pv210_rate_to_clk()
Dphy-exynos4210-usb2.c108 case 12 * MHZ: in exynos4210_rate_to_clk()
111 case 24 * MHZ: in exynos4210_rate_to_clk()
114 case 48 * MHZ: in exynos4210_rate_to_clk()
Dphy-exynos5-usbdrd.c150 #define MHZ (KHZ * KHZ) macro
233 case 10 * MHZ: in exynos5_rate_to_clk()
236 case 12 * MHZ: in exynos5_rate_to_clk()
242 case 20 * MHZ: in exynos5_rate_to_clk()
245 case 24 * MHZ: in exynos5_rate_to_clk()
248 case 50 * MHZ: in exynos5_rate_to_clk()
Dphy-samsung-usb2.h20 #define MHZ (KHZ * KHZ) macro
/drivers/clk/hisilicon/
Dclk-hi3660-stub.c25 #define MHZ (1000 * 1000) macro
66 stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ; in hi3660_stub_clk_recalc_rate()
86 stub_clk->msg[1] = rate / MHZ; in hi3660_stub_clk_set_rate()
/drivers/soc/samsung/
Dexynos-asv.c26 #define MHZ 1000000U macro
52 opp = dev_pm_opp_find_freq_exact(cpu, opp_freq * MHZ, true); in exynos_asv_update_cpu_opps()
67 ret = dev_pm_opp_adjust_voltage(cpu, opp_freq * MHZ, in exynos_asv_update_cpu_opps()
/drivers/mfd/
Dsm501.c86 #define MHZ (1000 * 1000) macro
121 pll2 = 288 * MHZ; in decode_div()
126 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
1538 .mclk = 72 * MHZ,
[all …]
/drivers/spi/
Dspi-ath79.c27 #define MHZ (1000 * 1000) macro
186 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); in ath79_spi_probe()

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