• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Freescale i.MX7 SoC series MIPI-CSI V3.3 receiver driver
4  *
5  * Copyright (C) 2019 Linaro Ltd
6  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
7  * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
8  *
9  */
10 
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/of.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/reset.h>
25 #include <linux/spinlock.h>
26 
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-mc.h>
30 #include <media/v4l2-subdev.h>
31 
32 #define CSIS_DRIVER_NAME			"imx7-mipi-csis"
33 #define CSIS_SUBDEV_NAME			CSIS_DRIVER_NAME
34 
35 #define CSIS_PAD_SINK				0
36 #define CSIS_PAD_SOURCE				1
37 #define CSIS_PADS_NUM				2
38 
39 #define MIPI_CSIS_DEF_PIX_WIDTH			640
40 #define MIPI_CSIS_DEF_PIX_HEIGHT		480
41 
42 /* Register map definition */
43 
44 /* CSIS common control */
45 #define MIPI_CSIS_CMN_CTRL			0x04
46 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW	BIT(16)
47 #define MIPI_CSIS_CMN_CTRL_INTER_MODE		BIT(10)
48 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL	BIT(2)
49 #define MIPI_CSIS_CMN_CTRL_RESET		BIT(1)
50 #define MIPI_CSIS_CMN_CTRL_ENABLE		BIT(0)
51 
52 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET	8
53 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK		(3 << 8)
54 
55 /* CSIS clock control */
56 #define MIPI_CSIS_CLK_CTRL			0x08
57 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x)	((x) << 28)
58 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x)	((x) << 24)
59 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x)	((x) << 20)
60 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x)	((x) << 16)
61 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK	(0xf << 4)
62 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC		BIT(0)
63 
64 /* CSIS Interrupt mask */
65 #define MIPI_CSIS_INTMSK			0x10
66 #define MIPI_CSIS_INTMSK_EVEN_BEFORE		BIT(31)
67 #define MIPI_CSIS_INTMSK_EVEN_AFTER		BIT(30)
68 #define MIPI_CSIS_INTMSK_ODD_BEFORE		BIT(29)
69 #define MIPI_CSIS_INTMSK_ODD_AFTER		BIT(28)
70 #define MIPI_CSIS_INTMSK_FRAME_START		BIT(24)
71 #define MIPI_CSIS_INTMSK_FRAME_END		BIT(20)
72 #define MIPI_CSIS_INTMSK_ERR_SOT_HS		BIT(16)
73 #define MIPI_CSIS_INTMSK_ERR_LOST_FS		BIT(12)
74 #define MIPI_CSIS_INTMSK_ERR_LOST_FE		BIT(8)
75 #define MIPI_CSIS_INTMSK_ERR_OVER		BIT(4)
76 #define MIPI_CSIS_INTMSK_ERR_WRONG_CFG		BIT(3)
77 #define MIPI_CSIS_INTMSK_ERR_ECC		BIT(2)
78 #define MIPI_CSIS_INTMSK_ERR_CRC		BIT(1)
79 #define MIPI_CSIS_INTMSK_ERR_UNKNOWN		BIT(0)
80 
81 /* CSIS Interrupt source */
82 #define MIPI_CSIS_INTSRC			0x14
83 #define MIPI_CSIS_INTSRC_EVEN_BEFORE		BIT(31)
84 #define MIPI_CSIS_INTSRC_EVEN_AFTER		BIT(30)
85 #define MIPI_CSIS_INTSRC_EVEN			BIT(30)
86 #define MIPI_CSIS_INTSRC_ODD_BEFORE		BIT(29)
87 #define MIPI_CSIS_INTSRC_ODD_AFTER		BIT(28)
88 #define MIPI_CSIS_INTSRC_ODD			(0x3 << 28)
89 #define MIPI_CSIS_INTSRC_NON_IMAGE_DATA		(0xf << 28)
90 #define MIPI_CSIS_INTSRC_FRAME_START		BIT(24)
91 #define MIPI_CSIS_INTSRC_FRAME_END		BIT(20)
92 #define MIPI_CSIS_INTSRC_ERR_SOT_HS		BIT(16)
93 #define MIPI_CSIS_INTSRC_ERR_LOST_FS		BIT(12)
94 #define MIPI_CSIS_INTSRC_ERR_LOST_FE		BIT(8)
95 #define MIPI_CSIS_INTSRC_ERR_OVER		BIT(4)
96 #define MIPI_CSIS_INTSRC_ERR_WRONG_CFG		BIT(3)
97 #define MIPI_CSIS_INTSRC_ERR_ECC		BIT(2)
98 #define MIPI_CSIS_INTSRC_ERR_CRC		BIT(1)
99 #define MIPI_CSIS_INTSRC_ERR_UNKNOWN		BIT(0)
100 #define MIPI_CSIS_INTSRC_ERRORS			0xfffff
101 
102 /* D-PHY status control */
103 #define MIPI_CSIS_DPHYSTATUS			0x20
104 #define MIPI_CSIS_DPHYSTATUS_ULPS_DAT		BIT(8)
105 #define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT	BIT(4)
106 #define MIPI_CSIS_DPHYSTATUS_ULPS_CLK		BIT(1)
107 #define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK	BIT(0)
108 
109 /* D-PHY common control */
110 #define MIPI_CSIS_DPHYCTRL			0x24
111 #define MIPI_CSIS_DPHYCTRL_HSS_MASK		(0xff << 24)
112 #define MIPI_CSIS_DPHYCTRL_HSS_OFFSET		24
113 #define MIPI_CSIS_DPHYCTRL_SCLKS_MASK		(0x3 << 22)
114 #define MIPI_CSIS_DPHYCTRL_SCLKS_OFFSET		22
115 #define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK	BIT(6)
116 #define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT	BIT(5)
117 #define MIPI_CSIS_DPHYCTRL_ENABLE_DAT		BIT(1)
118 #define MIPI_CSIS_DPHYCTRL_ENABLE_CLK		BIT(0)
119 #define MIPI_CSIS_DPHYCTRL_ENABLE		(0x1f << 0)
120 
121 /* D-PHY Master and Slave Control register Low */
122 #define MIPI_CSIS_DPHYBCTRL_L			0x30
123 /* D-PHY Master and Slave Control register High */
124 #define MIPI_CSIS_DPHYBCTRL_H			0x34
125 /* D-PHY Slave Control register Low */
126 #define MIPI_CSIS_DPHYSCTRL_L			0x38
127 /* D-PHY Slave Control register High */
128 #define MIPI_CSIS_DPHYSCTRL_H			0x3c
129 
130 /* ISP Configuration register */
131 #define MIPI_CSIS_ISPCONFIG_CH0			0x40
132 #define MIPI_CSIS_ISPCONFIG_CH1			0x50
133 #define MIPI_CSIS_ISPCONFIG_CH2			0x60
134 #define MIPI_CSIS_ISPCONFIG_CH3			0x70
135 
136 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK	(0xff << 24)
137 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x)	((x) << 24)
138 #define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT		BIT(12)
139 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT		BIT(11)
140 #define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT	(0x1e << 2)
141 #define MIPI_CSIS_ISPCFG_FMT_RAW8		(0x2a << 2)
142 #define MIPI_CSIS_ISPCFG_FMT_RAW10		(0x2b << 2)
143 #define MIPI_CSIS_ISPCFG_FMT_RAW12		(0x2c << 2)
144 #define MIPI_CSIS_ISPCFG_FMT_RAW14		(0x2d << 2)
145 
146 /* User defined formats, x = 1...4 */
147 #define MIPI_CSIS_ISPCFG_FMT_USER(x)		((0x30 + (x) - 1) << 2)
148 #define MIPI_CSIS_ISPCFG_FMT_MASK		(0x3f << 2)
149 
150 /* ISP Image Resolution register */
151 #define MIPI_CSIS_ISPRESOL_CH0			0x44
152 #define MIPI_CSIS_ISPRESOL_CH1			0x54
153 #define MIPI_CSIS_ISPRESOL_CH2			0x64
154 #define MIPI_CSIS_ISPRESOL_CH3			0x74
155 #define CSIS_MAX_PIX_WIDTH			0xffff
156 #define CSIS_MAX_PIX_HEIGHT			0xffff
157 
158 /* ISP SYNC register */
159 #define MIPI_CSIS_ISPSYNC_CH0			0x48
160 #define MIPI_CSIS_ISPSYNC_CH1			0x58
161 #define MIPI_CSIS_ISPSYNC_CH2			0x68
162 #define MIPI_CSIS_ISPSYNC_CH3			0x78
163 
164 #define MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET	18
165 #define MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET	12
166 #define MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET	0
167 
168 /* Non-image packet data buffers */
169 #define MIPI_CSIS_PKTDATA_ODD			0x2000
170 #define MIPI_CSIS_PKTDATA_EVEN			0x3000
171 #define MIPI_CSIS_PKTDATA_SIZE			SZ_4K
172 
173 #define DEFAULT_SCLK_CSIS_FREQ			166000000UL
174 
175 enum {
176 	ST_POWERED	= 1,
177 	ST_STREAMING	= 2,
178 	ST_SUSPENDED	= 4,
179 };
180 
181 struct mipi_csis_event {
182 	u32 mask;
183 	const char * const name;
184 	unsigned int counter;
185 };
186 
187 static const struct mipi_csis_event mipi_csis_events[] = {
188 	/* Errors */
189 	{ MIPI_CSIS_INTSRC_ERR_SOT_HS,	"SOT Error" },
190 	{ MIPI_CSIS_INTSRC_ERR_LOST_FS,	"Lost Frame Start Error" },
191 	{ MIPI_CSIS_INTSRC_ERR_LOST_FE,	"Lost Frame End Error" },
192 	{ MIPI_CSIS_INTSRC_ERR_OVER,	"FIFO Overflow Error" },
193 	{ MIPI_CSIS_INTSRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
194 	{ MIPI_CSIS_INTSRC_ERR_ECC,	"ECC Error" },
195 	{ MIPI_CSIS_INTSRC_ERR_CRC,	"CRC Error" },
196 	{ MIPI_CSIS_INTSRC_ERR_UNKNOWN,	"Unknown Error" },
197 	/* Non-image data receive events */
198 	{ MIPI_CSIS_INTSRC_EVEN_BEFORE,	"Non-image data before even frame" },
199 	{ MIPI_CSIS_INTSRC_EVEN_AFTER,	"Non-image data after even frame" },
200 	{ MIPI_CSIS_INTSRC_ODD_BEFORE,	"Non-image data before odd frame" },
201 	{ MIPI_CSIS_INTSRC_ODD_AFTER,	"Non-image data after odd frame" },
202 	/* Frame start/end */
203 	{ MIPI_CSIS_INTSRC_FRAME_START,	"Frame Start" },
204 	{ MIPI_CSIS_INTSRC_FRAME_END,	"Frame End" },
205 };
206 
207 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
208 
209 static const char * const mipi_csis_clk_id[] = {"pclk", "wrap", "phy"};
210 
211 struct csis_hw_reset {
212 	struct regmap *src;
213 	u8 req_src;
214 	u8 rst_bit;
215 };
216 
217 struct csi_state {
218 	/* lock elements below */
219 	struct mutex lock;
220 	/* lock for event handler */
221 	spinlock_t slock;
222 	struct device *dev;
223 	struct media_pad pads[CSIS_PADS_NUM];
224 	struct v4l2_subdev mipi_sd;
225 	struct v4l2_async_notifier notifier;
226 	struct v4l2_subdev *src_sd;
227 
228 	u8 index;
229 	struct platform_device *pdev;
230 	struct phy *phy;
231 	void __iomem *regs;
232 	struct clk *wrap_clk;
233 	int irq;
234 	u32 flags;
235 
236 	struct dentry *debugfs_root;
237 	bool debug;
238 
239 	int num_clks;
240 	struct clk_bulk_data *clks;
241 
242 	u32 clk_frequency;
243 	u32 hs_settle;
244 
245 	struct reset_control *mrst;
246 
247 	const struct csis_pix_format *csis_fmt;
248 	struct v4l2_mbus_framefmt format_mbus;
249 
250 	struct v4l2_fwnode_bus_mipi_csi2 bus;
251 
252 	struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
253 
254 	struct csis_hw_reset hw_reset;
255 	struct regulator *mipi_phy_regulator;
256 };
257 
258 struct csis_pix_format {
259 	u32 code;
260 	u32 fmt_reg;
261 	u8 width;
262 };
263 
264 static const struct csis_pix_format mipi_csis_formats[] = {
265 	/* YUV formats. */
266 	{
267 		.code = MEDIA_BUS_FMT_UYVY8_2X8,
268 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
269 		.width = 8,
270 	}, {
271 		.code = MEDIA_BUS_FMT_UYVY10_2X10,
272 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
273 		.width = 10,
274 	},
275 	/* RAW (Bayer and greyscale) formats. */
276 	{
277 		.code = MEDIA_BUS_FMT_SBGGR8_1X8,
278 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
279 		.width = 8,
280 	}, {
281 		.code = MEDIA_BUS_FMT_SGBRG8_1X8,
282 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
283 		.width = 8,
284 	}, {
285 		.code = MEDIA_BUS_FMT_SGRBG8_1X8,
286 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
287 		.width = 8,
288 	}, {
289 		.code = MEDIA_BUS_FMT_SRGGB8_1X8,
290 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
291 		.width = 8,
292 	}, {
293 		.code = MEDIA_BUS_FMT_Y8_1X8,
294 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
295 		.width = 8,
296 	}, {
297 		.code = MEDIA_BUS_FMT_SBGGR10_1X10,
298 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
299 		.width = 10,
300 	}, {
301 		.code = MEDIA_BUS_FMT_SGBRG10_1X10,
302 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
303 		.width = 10,
304 	}, {
305 		.code = MEDIA_BUS_FMT_SGRBG10_1X10,
306 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
307 		.width = 10,
308 	}, {
309 		.code = MEDIA_BUS_FMT_SRGGB10_1X10,
310 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
311 		.width = 10,
312 	}, {
313 		.code = MEDIA_BUS_FMT_Y10_1X10,
314 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
315 		.width = 10,
316 	}, {
317 		.code = MEDIA_BUS_FMT_SBGGR12_1X12,
318 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
319 		.width = 12,
320 	}, {
321 		.code = MEDIA_BUS_FMT_SGBRG12_1X12,
322 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
323 		.width = 12,
324 	}, {
325 		.code = MEDIA_BUS_FMT_SGRBG12_1X12,
326 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
327 		.width = 12,
328 	}, {
329 		.code = MEDIA_BUS_FMT_SRGGB12_1X12,
330 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
331 		.width = 12,
332 	}, {
333 		.code = MEDIA_BUS_FMT_Y12_1X12,
334 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
335 		.width = 12,
336 	}, {
337 		.code = MEDIA_BUS_FMT_SBGGR14_1X14,
338 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
339 		.width = 14,
340 	}, {
341 		.code = MEDIA_BUS_FMT_SGBRG14_1X14,
342 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
343 		.width = 14,
344 	}, {
345 		.code = MEDIA_BUS_FMT_SGRBG14_1X14,
346 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
347 		.width = 14,
348 	}, {
349 		.code = MEDIA_BUS_FMT_SRGGB14_1X14,
350 		.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
351 		.width = 14,
352 	}
353 };
354 
355 #define mipi_csis_write(__csis, __r, __v) writel(__v, (__csis)->regs + (__r))
356 #define mipi_csis_read(__csis, __r) readl((__csis)->regs + (__r))
357 
mipi_csis_dump_regs(struct csi_state * state)358 static int mipi_csis_dump_regs(struct csi_state *state)
359 {
360 	struct device *dev = &state->pdev->dev;
361 	unsigned int i;
362 	u32 cfg;
363 	static const struct {
364 		u32 offset;
365 		const char * const name;
366 	} registers[] = {
367 		{ 0x04, "CTRL" },
368 		{ 0x24, "DPHYCTRL" },
369 		{ 0x08, "CLKCTRL" },
370 		{ 0x20, "DPHYSTS" },
371 		{ 0x10, "INTMSK" },
372 		{ 0x40, "CONFIG_CH0" },
373 		{ 0x44, "RESOL_CH0" },
374 		{ 0xC0, "DBG_CONFIG" },
375 		{ 0x38, "DPHYSLAVE_L" },
376 		{ 0x3C, "DPHYSLAVE_H" },
377 	};
378 
379 	dev_info(dev, "--- REGISTERS ---\n");
380 
381 	for (i = 0; i < ARRAY_SIZE(registers); i++) {
382 		cfg = mipi_csis_read(state, registers[i].offset);
383 		dev_info(dev, "%12s: 0x%08x\n", registers[i].name, cfg);
384 	}
385 
386 	return 0;
387 }
388 
389 static struct csi_state *
mipi_notifier_to_csis_state(struct v4l2_async_notifier * n)390 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n)
391 {
392 	return container_of(n, struct csi_state, notifier);
393 }
394 
mipi_sd_to_csis_state(struct v4l2_subdev * sdev)395 static struct csi_state *mipi_sd_to_csis_state(struct v4l2_subdev *sdev)
396 {
397 	return container_of(sdev, struct csi_state, mipi_sd);
398 }
399 
find_csis_format(u32 code)400 static const struct csis_pix_format *find_csis_format(u32 code)
401 {
402 	unsigned int i;
403 
404 	for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
405 		if (code == mipi_csis_formats[i].code)
406 			return &mipi_csis_formats[i];
407 	return NULL;
408 }
409 
mipi_csis_enable_interrupts(struct csi_state * state,bool on)410 static void mipi_csis_enable_interrupts(struct csi_state *state, bool on)
411 {
412 	mipi_csis_write(state, MIPI_CSIS_INTMSK, on ? 0xffffffff : 0);
413 }
414 
mipi_csis_sw_reset(struct csi_state * state)415 static void mipi_csis_sw_reset(struct csi_state *state)
416 {
417 	u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
418 
419 	mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
420 			val | MIPI_CSIS_CMN_CTRL_RESET);
421 	usleep_range(10, 20);
422 }
423 
mipi_csis_phy_init(struct csi_state * state)424 static int mipi_csis_phy_init(struct csi_state *state)
425 {
426 	state->mipi_phy_regulator = devm_regulator_get(state->dev, "phy");
427 	if (IS_ERR(state->mipi_phy_regulator))
428 		return PTR_ERR(state->mipi_phy_regulator);
429 
430 	return regulator_set_voltage(state->mipi_phy_regulator, 1000000,
431 				     1000000);
432 }
433 
mipi_csis_phy_reset(struct csi_state * state)434 static void mipi_csis_phy_reset(struct csi_state *state)
435 {
436 	reset_control_assert(state->mrst);
437 
438 	msleep(20);
439 
440 	reset_control_deassert(state->mrst);
441 }
442 
mipi_csis_system_enable(struct csi_state * state,int on)443 static void mipi_csis_system_enable(struct csi_state *state, int on)
444 {
445 	u32 val, mask;
446 
447 	val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
448 	if (on)
449 		val |= MIPI_CSIS_CMN_CTRL_ENABLE;
450 	else
451 		val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
452 	mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
453 
454 	val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
455 	val &= ~MIPI_CSIS_DPHYCTRL_ENABLE;
456 	if (on) {
457 		mask = (1 << (state->bus.num_data_lanes + 1)) - 1;
458 		val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE);
459 	}
460 	mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
461 }
462 
463 /* Called with the state.lock mutex held */
__mipi_csis_set_format(struct csi_state * state)464 static void __mipi_csis_set_format(struct csi_state *state)
465 {
466 	struct v4l2_mbus_framefmt *mf = &state->format_mbus;
467 	u32 val;
468 
469 	/* Color format */
470 	val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);
471 	val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK);
472 	val |= state->csis_fmt->fmt_reg;
473 	mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
474 
475 	/* Pixel resolution */
476 	val = mf->width | (mf->height << 16);
477 	mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val);
478 }
479 
mipi_csis_set_hsync_settle(struct csi_state * state,int hs_settle)480 static void mipi_csis_set_hsync_settle(struct csi_state *state, int hs_settle)
481 {
482 	u32 val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
483 
484 	val = (val & ~MIPI_CSIS_DPHYCTRL_HSS_MASK) | (hs_settle << 24);
485 
486 	mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
487 }
488 
mipi_csis_set_params(struct csi_state * state)489 static void mipi_csis_set_params(struct csi_state *state)
490 {
491 	int lanes = state->bus.num_data_lanes;
492 	u32 val;
493 
494 	val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
495 	val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
496 	val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
497 	val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
498 	mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
499 
500 	__mipi_csis_set_format(state);
501 
502 	mipi_csis_set_hsync_settle(state, state->hs_settle);
503 
504 	val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) |
505 		(0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) |
506 		(0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET);
507 	mipi_csis_write(state, MIPI_CSIS_ISPSYNC_CH0, val);
508 
509 	val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL);
510 	val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC;
511 	if (state->wrap_clk)
512 		val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
513 	else
514 		val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC;
515 
516 	val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
517 	val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
518 	mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val);
519 
520 	mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_L, 0x1f4);
521 	mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_H, 0);
522 
523 	/* Update the shadow register. */
524 	val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
525 	mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
526 			val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
527 			MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
528 }
529 
mipi_csis_clk_enable(struct csi_state * state)530 static int mipi_csis_clk_enable(struct csi_state *state)
531 {
532 	return clk_bulk_prepare_enable(state->num_clks, state->clks);
533 }
534 
mipi_csis_clk_disable(struct csi_state * state)535 static void mipi_csis_clk_disable(struct csi_state *state)
536 {
537 	clk_bulk_disable_unprepare(state->num_clks, state->clks);
538 }
539 
mipi_csis_clk_get(struct csi_state * state)540 static int mipi_csis_clk_get(struct csi_state *state)
541 {
542 	struct device *dev = &state->pdev->dev;
543 	unsigned int i;
544 	int ret;
545 
546 	state->num_clks = ARRAY_SIZE(mipi_csis_clk_id);
547 	state->clks = devm_kcalloc(dev, state->num_clks, sizeof(*state->clks),
548 				   GFP_KERNEL);
549 
550 	if (!state->clks)
551 		return -ENOMEM;
552 
553 	for (i = 0; i < state->num_clks; i++)
554 		state->clks[i].id = mipi_csis_clk_id[i];
555 
556 	ret = devm_clk_bulk_get(dev, state->num_clks, state->clks);
557 	if (ret < 0)
558 		return ret;
559 
560 	state->wrap_clk = devm_clk_get(dev, "wrap");
561 	if (IS_ERR(state->wrap_clk))
562 		return PTR_ERR(state->wrap_clk);
563 
564 	/* Set clock rate */
565 	ret = clk_set_rate(state->wrap_clk, state->clk_frequency);
566 	if (ret < 0)
567 		dev_err(dev, "set rate=%d failed: %d\n", state->clk_frequency,
568 			ret);
569 
570 	return ret;
571 }
572 
mipi_csis_start_stream(struct csi_state * state)573 static void mipi_csis_start_stream(struct csi_state *state)
574 {
575 	mipi_csis_sw_reset(state);
576 	mipi_csis_set_params(state);
577 	mipi_csis_system_enable(state, true);
578 	mipi_csis_enable_interrupts(state, true);
579 }
580 
mipi_csis_stop_stream(struct csi_state * state)581 static void mipi_csis_stop_stream(struct csi_state *state)
582 {
583 	mipi_csis_enable_interrupts(state, false);
584 	mipi_csis_system_enable(state, false);
585 }
586 
mipi_csis_clear_counters(struct csi_state * state)587 static void mipi_csis_clear_counters(struct csi_state *state)
588 {
589 	unsigned long flags;
590 	unsigned int i;
591 
592 	spin_lock_irqsave(&state->slock, flags);
593 	for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
594 		state->events[i].counter = 0;
595 	spin_unlock_irqrestore(&state->slock, flags);
596 }
597 
mipi_csis_log_counters(struct csi_state * state,bool non_errors)598 static void mipi_csis_log_counters(struct csi_state *state, bool non_errors)
599 {
600 	unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
601 				: MIPI_CSIS_NUM_EVENTS - 6;
602 	struct device *dev = &state->pdev->dev;
603 	unsigned long flags;
604 	unsigned int i;
605 
606 	spin_lock_irqsave(&state->slock, flags);
607 
608 	for (i = 0; i < num_events; ++i) {
609 		if (state->events[i].counter > 0 || state->debug)
610 			dev_info(dev, "%s events: %d\n", state->events[i].name,
611 				 state->events[i].counter);
612 	}
613 	spin_unlock_irqrestore(&state->slock, flags);
614 }
615 
616 /*
617  * V4L2 subdev operations
618  */
mipi_csis_s_stream(struct v4l2_subdev * mipi_sd,int enable)619 static int mipi_csis_s_stream(struct v4l2_subdev *mipi_sd, int enable)
620 {
621 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
622 	int ret = 0;
623 
624 	if (enable) {
625 		mipi_csis_clear_counters(state);
626 		ret = pm_runtime_get_sync(&state->pdev->dev);
627 		if (ret < 0) {
628 			pm_runtime_put_noidle(&state->pdev->dev);
629 			return ret;
630 		}
631 		ret = v4l2_subdev_call(state->src_sd, core, s_power, 1);
632 		if (ret < 0)
633 			return ret;
634 	}
635 
636 	mutex_lock(&state->lock);
637 	if (enable) {
638 		if (state->flags & ST_SUSPENDED) {
639 			ret = -EBUSY;
640 			goto unlock;
641 		}
642 
643 		mipi_csis_start_stream(state);
644 		ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
645 		if (ret < 0)
646 			goto unlock;
647 
648 		mipi_csis_log_counters(state, true);
649 
650 		state->flags |= ST_STREAMING;
651 	} else {
652 		v4l2_subdev_call(state->src_sd, video, s_stream, 0);
653 		ret = v4l2_subdev_call(state->src_sd, core, s_power, 0);
654 		mipi_csis_stop_stream(state);
655 		state->flags &= ~ST_STREAMING;
656 		if (state->debug)
657 			mipi_csis_log_counters(state, true);
658 	}
659 
660 unlock:
661 	mutex_unlock(&state->lock);
662 	if (!enable)
663 		pm_runtime_put(&state->pdev->dev);
664 
665 	return ret;
666 }
667 
mipi_csis_link_setup(struct media_entity * entity,const struct media_pad * local_pad,const struct media_pad * remote_pad,u32 flags)668 static int mipi_csis_link_setup(struct media_entity *entity,
669 				const struct media_pad *local_pad,
670 				const struct media_pad *remote_pad, u32 flags)
671 {
672 	struct v4l2_subdev *mipi_sd = media_entity_to_v4l2_subdev(entity);
673 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
674 	struct v4l2_subdev *remote_sd;
675 	int ret = 0;
676 
677 	dev_dbg(state->dev, "link setup %s -> %s", remote_pad->entity->name,
678 		local_pad->entity->name);
679 
680 	remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
681 
682 	mutex_lock(&state->lock);
683 
684 	if (local_pad->flags & MEDIA_PAD_FL_SINK) {
685 		if (flags & MEDIA_LNK_FL_ENABLED) {
686 			if (state->src_sd) {
687 				ret = -EBUSY;
688 				goto out;
689 			}
690 			state->src_sd = remote_sd;
691 		} else {
692 			state->src_sd = NULL;
693 		}
694 	}
695 
696 out:
697 	mutex_unlock(&state->lock);
698 	return ret;
699 }
700 
701 static struct v4l2_mbus_framefmt *
mipi_csis_get_format(struct csi_state * state,struct v4l2_subdev_pad_config * cfg,enum v4l2_subdev_format_whence which,unsigned int pad)702 mipi_csis_get_format(struct csi_state *state,
703 		     struct v4l2_subdev_pad_config *cfg,
704 		     enum v4l2_subdev_format_whence which,
705 		     unsigned int pad)
706 {
707 	if (which == V4L2_SUBDEV_FORMAT_TRY)
708 		return v4l2_subdev_get_try_format(&state->mipi_sd, cfg, pad);
709 
710 	return &state->format_mbus;
711 }
712 
mipi_csis_init_cfg(struct v4l2_subdev * mipi_sd,struct v4l2_subdev_pad_config * cfg)713 static int mipi_csis_init_cfg(struct v4l2_subdev *mipi_sd,
714 			      struct v4l2_subdev_pad_config *cfg)
715 {
716 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
717 	struct v4l2_mbus_framefmt *fmt_sink;
718 	struct v4l2_mbus_framefmt *fmt_source;
719 	enum v4l2_subdev_format_whence which;
720 
721 	which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
722 	fmt_sink = mipi_csis_get_format(state, cfg, which, CSIS_PAD_SINK);
723 
724 	fmt_sink->code = MEDIA_BUS_FMT_UYVY8_2X8;
725 	fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH;
726 	fmt_sink->height = MIPI_CSIS_DEF_PIX_HEIGHT;
727 	fmt_sink->field = V4L2_FIELD_NONE;
728 
729 	fmt_sink->colorspace = V4L2_COLORSPACE_SMPTE170M;
730 	fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace);
731 	fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace);
732 	fmt_sink->quantization =
733 		V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace,
734 					      fmt_sink->ycbcr_enc);
735 
736 	/*
737 	 * When called from mipi_csis_subdev_init() to initialize the active
738 	 * configuration, cfg is NULL, which indicates there's no source pad
739 	 * configuration to set.
740 	 */
741 	if (!cfg)
742 		return 0;
743 
744 	fmt_source = mipi_csis_get_format(state, cfg, which, CSIS_PAD_SOURCE);
745 	*fmt_source = *fmt_sink;
746 
747 	return 0;
748 }
749 
mipi_csis_get_fmt(struct v4l2_subdev * mipi_sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * sdformat)750 static int mipi_csis_get_fmt(struct v4l2_subdev *mipi_sd,
751 			     struct v4l2_subdev_pad_config *cfg,
752 			     struct v4l2_subdev_format *sdformat)
753 {
754 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
755 	struct v4l2_mbus_framefmt *fmt;
756 
757 	mutex_lock(&state->lock);
758 	fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
759 	sdformat->format = *fmt;
760 	mutex_unlock(&state->lock);
761 
762 	return 0;
763 }
764 
mipi_csis_enum_mbus_code(struct v4l2_subdev * mipi_sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)765 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *mipi_sd,
766 				    struct v4l2_subdev_pad_config *cfg,
767 				    struct v4l2_subdev_mbus_code_enum *code)
768 {
769 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
770 
771 	/*
772 	 * The CSIS can't transcode in any way, the source format is identical
773 	 * to the sink format.
774 	 */
775 	if (code->pad == CSIS_PAD_SOURCE) {
776 		struct v4l2_mbus_framefmt *fmt;
777 
778 		if (code->index > 0)
779 			return -EINVAL;
780 
781 		fmt = mipi_csis_get_format(state, cfg, code->which, code->pad);
782 		code->code = fmt->code;
783 		return 0;
784 	}
785 
786 	if (code->pad != CSIS_PAD_SINK)
787 		return -EINVAL;
788 
789 	if (code->index >= ARRAY_SIZE(mipi_csis_formats))
790 		return -EINVAL;
791 
792 	code->code = mipi_csis_formats[code->index].code;
793 
794 	return 0;
795 }
796 
mipi_csis_set_fmt(struct v4l2_subdev * mipi_sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * sdformat)797 static int mipi_csis_set_fmt(struct v4l2_subdev *mipi_sd,
798 			     struct v4l2_subdev_pad_config *cfg,
799 			     struct v4l2_subdev_format *sdformat)
800 {
801 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
802 	struct csis_pix_format const *csis_fmt;
803 	struct v4l2_mbus_framefmt *fmt;
804 	unsigned int align;
805 
806 	/*
807 	 * The CSIS can't transcode in any way, the source format can't be
808 	 * modified.
809 	 */
810 	if (sdformat->pad == CSIS_PAD_SOURCE)
811 		return mipi_csis_get_fmt(mipi_sd, cfg, sdformat);
812 
813 	if (sdformat->pad != CSIS_PAD_SINK)
814 		return -EINVAL;
815 
816 	fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
817 
818 	mutex_lock(&state->lock);
819 
820 	/* Validate the media bus code and clamp the size. */
821 	csis_fmt = find_csis_format(sdformat->format.code);
822 	if (!csis_fmt)
823 		csis_fmt = &mipi_csis_formats[0];
824 
825 	fmt->code = csis_fmt->code;
826 	fmt->width = sdformat->format.width;
827 	fmt->height = sdformat->format.height;
828 
829 	/*
830 	 * The total number of bits per line must be a multiple of 8. We thus
831 	 * need to align the width for formats that are not multiples of 8
832 	 * bits.
833 	 */
834 	switch (csis_fmt->width % 8) {
835 	case 0:
836 		align = 1;
837 		break;
838 	case 4:
839 		align = 2;
840 		break;
841 	case 2:
842 	case 6:
843 		align = 4;
844 		break;
845 	case 1:
846 	case 3:
847 	case 5:
848 	case 7:
849 		align = 8;
850 		break;
851 	}
852 
853 	v4l_bound_align_image(&fmt->width, 1, CSIS_MAX_PIX_WIDTH, align,
854 			      &fmt->height, 1, CSIS_MAX_PIX_HEIGHT, 1, 0);
855 
856 	sdformat->format = *fmt;
857 
858 	/* Propagate the format from sink to source. */
859 	fmt = mipi_csis_get_format(state, cfg, sdformat->which,
860 				   CSIS_PAD_SOURCE);
861 	*fmt = sdformat->format;
862 
863 	/* Store the CSIS format descriptor for active formats. */
864 	if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
865 		state->csis_fmt = csis_fmt;
866 
867 	mutex_unlock(&state->lock);
868 
869 	return 0;
870 }
871 
mipi_csis_log_status(struct v4l2_subdev * mipi_sd)872 static int mipi_csis_log_status(struct v4l2_subdev *mipi_sd)
873 {
874 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
875 
876 	mutex_lock(&state->lock);
877 	mipi_csis_log_counters(state, true);
878 	if (state->debug && (state->flags & ST_POWERED))
879 		mipi_csis_dump_regs(state);
880 	mutex_unlock(&state->lock);
881 
882 	return 0;
883 }
884 
mipi_csis_irq_handler(int irq,void * dev_id)885 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
886 {
887 	struct csi_state *state = dev_id;
888 	unsigned long flags;
889 	unsigned int i;
890 	u32 status;
891 
892 	status = mipi_csis_read(state, MIPI_CSIS_INTSRC);
893 
894 	spin_lock_irqsave(&state->slock, flags);
895 
896 	/* Update the event/error counters */
897 	if ((status & MIPI_CSIS_INTSRC_ERRORS) || state->debug) {
898 		for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
899 			if (!(status & state->events[i].mask))
900 				continue;
901 			state->events[i].counter++;
902 		}
903 	}
904 	spin_unlock_irqrestore(&state->slock, flags);
905 
906 	mipi_csis_write(state, MIPI_CSIS_INTSRC, status);
907 
908 	return IRQ_HANDLED;
909 }
910 
911 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
912 	.log_status	= mipi_csis_log_status,
913 };
914 
915 static const struct media_entity_operations mipi_csis_entity_ops = {
916 	.link_setup	= mipi_csis_link_setup,
917 	.link_validate	= v4l2_subdev_link_validate,
918 	.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
919 };
920 
921 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
922 	.s_stream	= mipi_csis_s_stream,
923 };
924 
925 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
926 	.init_cfg		= mipi_csis_init_cfg,
927 	.enum_mbus_code		= mipi_csis_enum_mbus_code,
928 	.get_fmt		= mipi_csis_get_fmt,
929 	.set_fmt		= mipi_csis_set_fmt,
930 };
931 
932 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
933 	.core	= &mipi_csis_core_ops,
934 	.video	= &mipi_csis_video_ops,
935 	.pad	= &mipi_csis_pad_ops,
936 };
937 
mipi_csis_parse_dt(struct platform_device * pdev,struct csi_state * state)938 static int mipi_csis_parse_dt(struct platform_device *pdev,
939 			      struct csi_state *state)
940 {
941 	struct device_node *node = pdev->dev.of_node;
942 
943 	if (of_property_read_u32(node, "clock-frequency",
944 				 &state->clk_frequency))
945 		state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
946 
947 	/* Get MIPI PHY resets */
948 	state->mrst = devm_reset_control_get_exclusive(&pdev->dev, "mrst");
949 	if (IS_ERR(state->mrst))
950 		return PTR_ERR(state->mrst);
951 
952 	/* Get MIPI CSI-2 bus configuration from the endpoint node. */
953 	of_property_read_u32(node, "fsl,csis-hs-settle", &state->hs_settle);
954 
955 	return 0;
956 }
957 
958 static int mipi_csis_pm_resume(struct device *dev, bool runtime);
959 
mipi_csis_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_subdev * asd)960 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier,
961 				  struct v4l2_subdev *sd,
962 				  struct v4l2_async_subdev *asd)
963 {
964 	struct csi_state *state = mipi_notifier_to_csis_state(notifier);
965 	struct media_pad *sink = &state->mipi_sd.entity.pads[CSIS_PAD_SINK];
966 
967 	return v4l2_create_fwnode_links_to_pad(sd, sink);
968 }
969 
970 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = {
971 	.bound = mipi_csis_notify_bound,
972 };
973 
mipi_csis_subdev_init(struct v4l2_subdev * mipi_sd,struct platform_device * pdev,const struct v4l2_subdev_ops * ops)974 static int mipi_csis_subdev_init(struct v4l2_subdev *mipi_sd,
975 				 struct platform_device *pdev,
976 				 const struct v4l2_subdev_ops *ops)
977 {
978 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
979 
980 	v4l2_subdev_init(mipi_sd, ops);
981 	mipi_sd->owner = THIS_MODULE;
982 	snprintf(mipi_sd->name, sizeof(mipi_sd->name), "%s.%d",
983 		 CSIS_SUBDEV_NAME, state->index);
984 
985 	mipi_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
986 	mipi_sd->ctrl_handler = NULL;
987 
988 	mipi_sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
989 	mipi_sd->entity.ops = &mipi_csis_entity_ops;
990 
991 	mipi_sd->dev = &pdev->dev;
992 
993 	state->csis_fmt = &mipi_csis_formats[0];
994 	mipi_csis_init_cfg(mipi_sd, NULL);
995 
996 	v4l2_set_subdevdata(mipi_sd, &pdev->dev);
997 
998 	state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
999 	state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1000 	return media_entity_pads_init(&mipi_sd->entity, CSIS_PADS_NUM,
1001 				      state->pads);
1002 }
1003 
mipi_csis_async_register(struct csi_state * state)1004 static int mipi_csis_async_register(struct csi_state *state)
1005 {
1006 	struct v4l2_fwnode_endpoint vep = {
1007 		.bus_type = V4L2_MBUS_CSI2_DPHY,
1008 	};
1009 	struct v4l2_async_subdev *asd;
1010 	struct fwnode_handle *ep;
1011 	int ret;
1012 
1013 	v4l2_async_notifier_init(&state->notifier);
1014 
1015 	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0,
1016 					     FWNODE_GRAPH_ENDPOINT_NEXT);
1017 	if (!ep)
1018 		return -ENOTCONN;
1019 
1020 	ret = v4l2_fwnode_endpoint_parse(ep, &vep);
1021 	if (ret)
1022 		goto err_parse;
1023 
1024 	state->bus = vep.bus.mipi_csi2;
1025 
1026 	dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes);
1027 	dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags);
1028 
1029 	asd = v4l2_async_notifier_add_fwnode_remote_subdev(
1030 		&state->notifier, ep, sizeof(*asd));
1031 	if (IS_ERR(asd)) {
1032 		ret = PTR_ERR(asd);
1033 		goto err_parse;
1034 	}
1035 
1036 	fwnode_handle_put(ep);
1037 
1038 	state->notifier.ops = &mipi_csis_notify_ops;
1039 
1040 	ret = v4l2_async_subdev_notifier_register(&state->mipi_sd,
1041 						  &state->notifier);
1042 	if (ret)
1043 		return ret;
1044 
1045 	return v4l2_async_register_subdev(&state->mipi_sd);
1046 
1047 err_parse:
1048 	fwnode_handle_put(ep);
1049 
1050 	return ret;
1051 }
1052 
mipi_csis_dump_regs_show(struct seq_file * m,void * private)1053 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
1054 {
1055 	struct csi_state *state = m->private;
1056 
1057 	return mipi_csis_dump_regs(state);
1058 }
1059 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
1060 
mipi_csis_debugfs_init(struct csi_state * state)1061 static void mipi_csis_debugfs_init(struct csi_state *state)
1062 {
1063 	state->debugfs_root = debugfs_create_dir(dev_name(state->dev), NULL);
1064 
1065 	debugfs_create_bool("debug_enable", 0600, state->debugfs_root,
1066 			    &state->debug);
1067 	debugfs_create_file("dump_regs", 0600, state->debugfs_root, state,
1068 			    &mipi_csis_dump_regs_fops);
1069 }
1070 
mipi_csis_debugfs_exit(struct csi_state * state)1071 static void mipi_csis_debugfs_exit(struct csi_state *state)
1072 {
1073 	debugfs_remove_recursive(state->debugfs_root);
1074 }
1075 
mipi_csis_probe(struct platform_device * pdev)1076 static int mipi_csis_probe(struct platform_device *pdev)
1077 {
1078 	struct device *dev = &pdev->dev;
1079 	struct csi_state *state;
1080 	int ret;
1081 
1082 	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1083 	if (!state)
1084 		return -ENOMEM;
1085 
1086 	spin_lock_init(&state->slock);
1087 
1088 	state->pdev = pdev;
1089 	state->dev = dev;
1090 
1091 	ret = mipi_csis_parse_dt(pdev, state);
1092 	if (ret < 0) {
1093 		dev_err(dev, "Failed to parse device tree: %d\n", ret);
1094 		return ret;
1095 	}
1096 
1097 	ret = mipi_csis_phy_init(state);
1098 	if (ret < 0)
1099 		return ret;
1100 
1101 	mipi_csis_phy_reset(state);
1102 
1103 	state->regs = devm_platform_ioremap_resource(pdev, 0);
1104 	if (IS_ERR(state->regs))
1105 		return PTR_ERR(state->regs);
1106 
1107 	state->irq = platform_get_irq(pdev, 0);
1108 	if (state->irq < 0)
1109 		return state->irq;
1110 
1111 	ret = mipi_csis_clk_get(state);
1112 	if (ret < 0)
1113 		return ret;
1114 
1115 	ret = mipi_csis_clk_enable(state);
1116 	if (ret < 0) {
1117 		dev_err(state->dev, "failed to enable clocks: %d\n", ret);
1118 		return ret;
1119 	}
1120 
1121 	ret = devm_request_irq(dev, state->irq, mipi_csis_irq_handler,
1122 			       0, dev_name(dev), state);
1123 	if (ret) {
1124 		dev_err(dev, "Interrupt request failed\n");
1125 		goto disable_clock;
1126 	}
1127 
1128 	platform_set_drvdata(pdev, &state->mipi_sd);
1129 
1130 	mutex_init(&state->lock);
1131 	ret = mipi_csis_subdev_init(&state->mipi_sd, pdev,
1132 				    &mipi_csis_subdev_ops);
1133 	if (ret < 0)
1134 		goto disable_clock;
1135 
1136 	ret = mipi_csis_async_register(state);
1137 	if (ret < 0) {
1138 		dev_err(&pdev->dev, "async register failed: %d\n", ret);
1139 		goto cleanup;
1140 	}
1141 
1142 	memcpy(state->events, mipi_csis_events, sizeof(state->events));
1143 
1144 	mipi_csis_debugfs_init(state);
1145 	pm_runtime_enable(dev);
1146 	if (!pm_runtime_enabled(dev)) {
1147 		ret = mipi_csis_pm_resume(dev, true);
1148 		if (ret < 0)
1149 			goto unregister_all;
1150 	}
1151 
1152 	dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n",
1153 		 state->bus.num_data_lanes, state->hs_settle,
1154 		 state->wrap_clk ? 1 : 0, state->clk_frequency);
1155 
1156 	return 0;
1157 
1158 unregister_all:
1159 	mipi_csis_debugfs_exit(state);
1160 cleanup:
1161 	media_entity_cleanup(&state->mipi_sd.entity);
1162 	v4l2_async_notifier_unregister(&state->notifier);
1163 	v4l2_async_notifier_cleanup(&state->notifier);
1164 	v4l2_async_unregister_subdev(&state->mipi_sd);
1165 disable_clock:
1166 	mipi_csis_clk_disable(state);
1167 	mutex_destroy(&state->lock);
1168 
1169 	return ret;
1170 }
1171 
mipi_csis_pm_suspend(struct device * dev,bool runtime)1172 static int mipi_csis_pm_suspend(struct device *dev, bool runtime)
1173 {
1174 	struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
1175 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1176 	int ret = 0;
1177 
1178 	mutex_lock(&state->lock);
1179 	if (state->flags & ST_POWERED) {
1180 		mipi_csis_stop_stream(state);
1181 		ret = regulator_disable(state->mipi_phy_regulator);
1182 		if (ret)
1183 			goto unlock;
1184 		mipi_csis_clk_disable(state);
1185 		state->flags &= ~ST_POWERED;
1186 		if (!runtime)
1187 			state->flags |= ST_SUSPENDED;
1188 	}
1189 
1190 unlock:
1191 	mutex_unlock(&state->lock);
1192 
1193 	return ret ? -EAGAIN : 0;
1194 }
1195 
mipi_csis_pm_resume(struct device * dev,bool runtime)1196 static int mipi_csis_pm_resume(struct device *dev, bool runtime)
1197 {
1198 	struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
1199 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1200 	int ret = 0;
1201 
1202 	mutex_lock(&state->lock);
1203 	if (!runtime && !(state->flags & ST_SUSPENDED))
1204 		goto unlock;
1205 
1206 	if (!(state->flags & ST_POWERED)) {
1207 		ret = regulator_enable(state->mipi_phy_regulator);
1208 		if (ret)
1209 			goto unlock;
1210 
1211 		state->flags |= ST_POWERED;
1212 		mipi_csis_clk_enable(state);
1213 	}
1214 	if (state->flags & ST_STREAMING)
1215 		mipi_csis_start_stream(state);
1216 
1217 	state->flags &= ~ST_SUSPENDED;
1218 
1219 unlock:
1220 	mutex_unlock(&state->lock);
1221 
1222 	return ret ? -EAGAIN : 0;
1223 }
1224 
mipi_csis_suspend(struct device * dev)1225 static int __maybe_unused mipi_csis_suspend(struct device *dev)
1226 {
1227 	return mipi_csis_pm_suspend(dev, false);
1228 }
1229 
mipi_csis_resume(struct device * dev)1230 static int __maybe_unused mipi_csis_resume(struct device *dev)
1231 {
1232 	return mipi_csis_pm_resume(dev, false);
1233 }
1234 
mipi_csis_runtime_suspend(struct device * dev)1235 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
1236 {
1237 	return mipi_csis_pm_suspend(dev, true);
1238 }
1239 
mipi_csis_runtime_resume(struct device * dev)1240 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
1241 {
1242 	return mipi_csis_pm_resume(dev, true);
1243 }
1244 
mipi_csis_remove(struct platform_device * pdev)1245 static int mipi_csis_remove(struct platform_device *pdev)
1246 {
1247 	struct v4l2_subdev *mipi_sd = platform_get_drvdata(pdev);
1248 	struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1249 
1250 	mipi_csis_debugfs_exit(state);
1251 	v4l2_async_notifier_unregister(&state->notifier);
1252 	v4l2_async_notifier_cleanup(&state->notifier);
1253 	v4l2_async_unregister_subdev(&state->mipi_sd);
1254 
1255 	pm_runtime_disable(&pdev->dev);
1256 	mipi_csis_pm_suspend(&pdev->dev, true);
1257 	mipi_csis_clk_disable(state);
1258 	media_entity_cleanup(&state->mipi_sd.entity);
1259 	mutex_destroy(&state->lock);
1260 	pm_runtime_set_suspended(&pdev->dev);
1261 
1262 	return 0;
1263 }
1264 
1265 static const struct dev_pm_ops mipi_csis_pm_ops = {
1266 	SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1267 			   NULL)
1268 	SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume)
1269 };
1270 
1271 static const struct of_device_id mipi_csis_of_match[] = {
1272 	{ .compatible = "fsl,imx7-mipi-csi2", },
1273 	{ /* sentinel */ },
1274 };
1275 MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1276 
1277 static struct platform_driver mipi_csis_driver = {
1278 	.probe		= mipi_csis_probe,
1279 	.remove		= mipi_csis_remove,
1280 	.driver		= {
1281 		.of_match_table = mipi_csis_of_match,
1282 		.name		= CSIS_DRIVER_NAME,
1283 		.pm		= &mipi_csis_pm_ops,
1284 	},
1285 };
1286 
1287 module_platform_driver(mipi_csis_driver);
1288 
1289 MODULE_DESCRIPTION("i.MX7 MIPI CSI-2 Receiver driver");
1290 MODULE_LICENSE("GPL v2");
1291 MODULE_ALIAS("platform:imx7-mipi-csi2");
1292