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Searched refs:MI_FLUSH_DW (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/i915/gt/
Dgen6_engine_cs.c185 cmd = MI_FLUSH_DW; in mi_flush_dw()
379 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; in gen6_emit_breadcrumb_xcs()
399 *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB | in gen7_emit_breadcrumb_xcs()
410 *cs++ = MI_FLUSH_DW; in gen7_emit_breadcrumb_xcs()
Dintel_gpu_commands.h147 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ macro
Dintel_engine.h289 *cs++ = (MI_FLUSH_DW + 1) | flags; in __gen8_emit_flush_dw()
Dintel_lrc.c4541 cmd = MI_FLUSH_DW + 1; in gen8_emit_flush()
4816 cmd = MI_FLUSH_DW + 1; in gen12_emit_flush()
/drivers/gpu/drm/i915/
Di915_cmd_parser.c337 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
381 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
418 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
481 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ),
/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_client_blt.c175 cmd = MI_FLUSH_DW; in prepare_blit()