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Searched refs:MI_FLUSH_DW_USE_GTT (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/gt/
Dgen6_engine_cs.c204 *cs++ = HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; in mi_flush_dw()
380 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; in gen6_emit_breadcrumb_xcs()
401 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; in gen7_emit_breadcrumb_xcs()
Dintel_gpu_commands.h154 #define MI_FLUSH_DW_USE_GTT (1<<2) macro
Dintel_engine.h307 gtt_offset | MI_FLUSH_DW_USE_GTT, in gen8_emit_ggtt_write()
/drivers/gpu/drm/i915/
Di915_cmd_parser.c345 .mask = MI_FLUSH_DW_USE_GTT,
389 .mask = MI_FLUSH_DW_USE_GTT,
426 .mask = MI_FLUSH_DW_USE_GTT,