Home
last modified time | relevance | path

Searched refs:MTL_Q_TQOMR (Results 1 – 4 of 4) sorted by relevance

/drivers/net/ethernet/synopsys/
Ddwc-xlgmac-hw.c517 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_enable_tx()
521 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_enable_tx()
554 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_disable_tx()
557 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_disable_tx()
1523 MTL_Q_TQOMR)); in xlgmac_config_queue_mapping()
1529 MTL_Q_TQOMR)); in xlgmac_config_queue_mapping()
1537 MTL_Q_TQOMR)); in xlgmac_config_queue_mapping()
1543 MTL_Q_TQOMR)); in xlgmac_config_queue_mapping()
1641 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tx_fifo_size()
1644 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tx_fifo_size()
[all …]
Ddwc-xlgmac-reg.h393 #define MTL_Q_TQOMR 0x00 macro
/drivers/net/ethernet/amd/xgbe/
Dxgbe-dev.c237 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); in xgbe_config_tsf_mode()
259 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); in xgbe_config_tx_threshold()
2210 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); in xgbe_flush_tx_queues()
2216 MTL_Q_TQOMR, FTQ)) in xgbe_flush_tx_queues()
2557 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); in xgbe_config_tx_fifo_size()
2625 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
2633 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
3303 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, in xgbe_enable_tx()
3323 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); in xgbe_disable_tx()
Dxgbe-common.h802 #define MTL_Q_TQOMR 0x00 macro