| /drivers/gpu/drm/amd/include/asic_reg/bif/ |
| D | bif_5_1_enum.h | 990 typedef enum MTYPE { enum
995 } MTYPE; typedef
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| D | bif_5_0_enum.h | 1120 typedef enum MTYPE { enum
1125 } MTYPE; typedef
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| /drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_8_2_enum.h | 990 typedef enum MTYPE { enum
995 } MTYPE; typedef
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| D | gmc_8_1_enum.h | 1120 typedef enum MTYPE { enum
1125 } MTYPE; typedef
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| /drivers/gpu/drm/amd/include/asic_reg/smu/ |
| D | smu_8_0_enum.h | 990 typedef enum MTYPE { enum
995 } MTYPE; typedef
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| D | smu_7_1_3_enum.h | 1204 typedef enum MTYPE { enum
1209 } MTYPE; typedef
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| D | smu_7_1_2_enum.h | 1168 typedef enum MTYPE { enum
1173 } MTYPE; typedef
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| D | smu_7_1_1_enum.h | 1150 typedef enum MTYPE { enum
1155 } MTYPE; typedef
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| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_6_0_enum.h | 1003 typedef enum MTYPE { enum
1008 } MTYPE; typedef
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| D | uvd_5_0_enum.h | 1133 typedef enum MTYPE { enum
1138 } MTYPE; typedef
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| /drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_2_4_enum.h | 1285 typedef enum MTYPE { enum
1290 } MTYPE; typedef
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| D | oss_3_0_1_enum.h | 1386 typedef enum MTYPE { enum
1391 } MTYPE; typedef
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| D | oss_3_0_enum.h | 1419 typedef enum MTYPE { enum
1424 } MTYPE; typedef
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| /drivers/gpu/drm/amd/include/asic_reg/dce/ |
| D | dce_10_0_enum.h | 1695 typedef enum MTYPE { enum
1700 } MTYPE; typedef
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| D | dce_11_0_enum.h | 5562 typedef enum MTYPE { enum
5567 } MTYPE; typedef
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 134 MTYPE, MTYPE_UC);/* XXX for emulation. */ in gfxhub_v1_0_init_tlb_regs()
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| D | gfxhub_v2_0.c | 202 MTYPE, MTYPE_UC); /* UC, uncached */ in gfxhub_v2_0_init_tlb_regs()
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| D | gfxhub_v2_1.c | 200 MTYPE, MTYPE_UC); /* UC, uncached */ in gfxhub_v2_1_init_tlb_regs()
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| D | mmhub_v2_0.c | 246 MTYPE, MTYPE_UC); /* UC, uncached */ in mmhub_v2_0_init_tlb_regs()
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| D | mmhub_v1_0.c | 151 MTYPE, MTYPE_UC);/* XXX for emulation. */ in mmhub_v1_0_init_tlb_regs()
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| D | mmhub_v9_4.c | 196 MTYPE, MTYPE_UC);/* XXX for emulation. */ in mmhub_v9_4_init_tlb_regs()
|
| D | gfx_v8_0.c | 4288 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); in gfx_v8_0_cp_gfx_resume()
4555 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3); in gfx_v8_0_mqd_init()
4559 tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3); in gfx_v8_0_mqd_init()
4563 tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3); in gfx_v8_0_mqd_init()
|
| /drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | smu8_smumgr.c | 203 tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1); in smu8_load_mec_firmware()
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| /drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_7_2_enum.h | 6228 typedef enum MTYPE { enum
6233 } MTYPE; typedef
|
| D | gfx_8_0_enum.h | 6780 typedef enum MTYPE { enum
6785 } MTYPE; typedef
|