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Searched refs:NV_RD32 (Results 1 – 10 of 10) sorted by relevance

/drivers/video/fbdev/riva/
Dnv_driver.c60 reg52C = NV_RD32(PRAMDAC, 0x052C); in riva_is_connected()
61 reg608 = NV_RD32(PRAMDAC, 0x0608); in riva_is_connected()
67 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1); in riva_is_connected()
74 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE; in riva_is_connected()
77 NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF); in riva_is_connected()
139 if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100) in riva_is_second()
145 if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100) in riva_is_second()
166 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) { in riva_get_memlen()
167 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_memlen()
168 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { in riva_get_memlen()
[all …]
Driva_hw.c65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv3Busy()
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); in nv3Busy()
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv4Busy()
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv4Busy()
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv10Busy()
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv10Busy()
621 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv3UpdateArbitrationSettings()
628 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv3UpdateArbitrationSettings()
810 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv4UpdateArbitrationSettings()
813 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv4UpdateArbitrationSettings()
[all …]
Dfbdev.c303 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; in riva_bl_update_status()
304 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC; in riva_bl_update_status()
784 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & in riva_load_video_mode()
791 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & in riva_load_video_mode()
793 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | in riva_load_video_mode()
799 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | in riva_load_video_mode()
801 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & in riva_load_video_mode()
804 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); in riva_load_video_mode()
Driva_hw.h83 #define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) macro
559 (hwinst).FifoFreeCount = NV_RD32(&(hwinst).hwptr->FifoFree, 0) >> 2; \
/drivers/video/fbdev/nvidia/
Dnv_hw.c83 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300)); in NVShowHideCursor()
147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
164 pll = NV_RD32(par->PMC, 0x4004); in nvGetClocks()
172 pll = NV_RD32(par->PRAMDAC0, 0x0504); in nvGetClocks()
176 pll = NV_RD32(par->PRAMDAC0, 0x0574); in nvGetClocks()
186 pll = NV_RD32(par->PRAMDAC0, 0x0500); in nvGetClocks()
190 pll = NV_RD32(par->PRAMDAC0, 0x0570); in nvGetClocks()
202 pll = NV_RD32(par->PRAMDAC0, 0x0504); in nvGetClocks()
[all …]
Dnv_setup.c150 dac0_reg608 = NV_RD32(PRAMDAC, 0x0608); in NVIsConnected()
154 reg52C = NV_RD32(PRAMDAC, 0x052C); in NVIsConnected()
155 reg608 = NV_RD32(PRAMDAC, 0x0608); in NVIsConnected()
161 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1); in NVIsConnected()
164 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) | in NVIsConnected()
169 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0; in NVIsConnected()
202 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) { in nv4GetConfig()
204 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 + in nv4GetConfig()
207 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) { in nv4GetConfig()
223 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ? in nv4GetConfig()
[all …]
Dnv_backlight.c63 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF; in nvidia_bl_update_status()
64 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC; in nvidia_bl_update_status()
65 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC; in nvidia_bl_update_status()
Dnvidia.c413 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff; in nvidia_calc_regs()
423 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828); in nvidia_calc_regs()
439 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000; in nvidia_calc_regs()
440 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000; in nvidia_calc_regs()
443 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); in nvidia_calc_regs()
445 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578); in nvidia_calc_regs()
447 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000; in nvidia_calc_regs()
448 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000; in nvidia_calc_regs()
450 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); in nvidia_calc_regs()
452 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); in nvidia_calc_regs()
[all …]
Dnv_local.h67 #define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) macro
96 #define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
Dnv_accel.c101 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ; in NVSync()