1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2003-2012 Broadcom Corporation 4 * All Rights Reserved 5 */ 6 7 /* #define MAC_SPLIT_MODE */ 8 9 #define MAC_SPACING 0x400 10 #define XGMAC_SPACING 0x400 11 12 /* PE-MCXMAC register and bit field definitions */ 13 #define R_MAC_CONFIG_1 0x00 14 #define O_MAC_CONFIG_1__srst 31 15 #define O_MAC_CONFIG_1__simr 30 16 #define O_MAC_CONFIG_1__hrrmc 18 17 #define W_MAC_CONFIG_1__hrtmc 2 18 #define O_MAC_CONFIG_1__hrrfn 16 19 #define W_MAC_CONFIG_1__hrtfn 2 20 #define O_MAC_CONFIG_1__intlb 8 21 #define O_MAC_CONFIG_1__rxfc 5 22 #define O_MAC_CONFIG_1__txfc 4 23 #define O_MAC_CONFIG_1__srxen 3 24 #define O_MAC_CONFIG_1__rxen 2 25 #define O_MAC_CONFIG_1__stxen 1 26 #define O_MAC_CONFIG_1__txen 0 27 #define R_MAC_CONFIG_2 0x01 28 #define O_MAC_CONFIG_2__prlen 12 29 #define W_MAC_CONFIG_2__prlen 4 30 #define O_MAC_CONFIG_2__speed 8 31 #define W_MAC_CONFIG_2__speed 2 32 #define O_MAC_CONFIG_2__hugen 5 33 #define O_MAC_CONFIG_2__flchk 4 34 #define O_MAC_CONFIG_2__crce 1 35 #define O_MAC_CONFIG_2__fulld 0 36 #define R_IPG_IFG 0x02 37 #define O_IPG_IFG__ipgr1 24 38 #define W_IPG_IFG__ipgr1 7 39 #define O_IPG_IFG__ipgr2 16 40 #define W_IPG_IFG__ipgr2 7 41 #define O_IPG_IFG__mifg 8 42 #define W_IPG_IFG__mifg 8 43 #define O_IPG_IFG__ipgt 0 44 #define W_IPG_IFG__ipgt 7 45 #define R_HALF_DUPLEX 0x03 46 #define O_HALF_DUPLEX__abebt 24 47 #define W_HALF_DUPLEX__abebt 4 48 #define O_HALF_DUPLEX__abebe 19 49 #define O_HALF_DUPLEX__bpnb 18 50 #define O_HALF_DUPLEX__nobo 17 51 #define O_HALF_DUPLEX__edxsdfr 16 52 #define O_HALF_DUPLEX__retry 12 53 #define W_HALF_DUPLEX__retry 4 54 #define O_HALF_DUPLEX__lcol 0 55 #define W_HALF_DUPLEX__lcol 10 56 #define R_MAXIMUM_FRAME_LENGTH 0x04 57 #define O_MAXIMUM_FRAME_LENGTH__maxf 0 58 #define W_MAXIMUM_FRAME_LENGTH__maxf 16 59 #define R_TEST 0x07 60 #define O_TEST__mbof 3 61 #define O_TEST__rthdf 2 62 #define O_TEST__tpause 1 63 #define O_TEST__sstct 0 64 #define R_MII_MGMT_CONFIG 0x08 65 #define O_MII_MGMT_CONFIG__scinc 5 66 #define O_MII_MGMT_CONFIG__spre 4 67 #define O_MII_MGMT_CONFIG__clks 3 68 #define W_MII_MGMT_CONFIG__clks 3 69 #define R_MII_MGMT_COMMAND 0x09 70 #define O_MII_MGMT_COMMAND__scan 1 71 #define O_MII_MGMT_COMMAND__rstat 0 72 #define R_MII_MGMT_ADDRESS 0x0A 73 #define O_MII_MGMT_ADDRESS__fiad 8 74 #define W_MII_MGMT_ADDRESS__fiad 5 75 #define O_MII_MGMT_ADDRESS__fgad 5 76 #define W_MII_MGMT_ADDRESS__fgad 0 77 #define R_MII_MGMT_WRITE_DATA 0x0B 78 #define O_MII_MGMT_WRITE_DATA__ctld 0 79 #define W_MII_MGMT_WRITE_DATA__ctld 16 80 #define R_MII_MGMT_STATUS 0x0C 81 #define R_MII_MGMT_INDICATORS 0x0D 82 #define O_MII_MGMT_INDICATORS__nvalid 2 83 #define O_MII_MGMT_INDICATORS__scan 1 84 #define O_MII_MGMT_INDICATORS__busy 0 85 #define R_INTERFACE_CONTROL 0x0E 86 #define O_INTERFACE_CONTROL__hrstint 31 87 #define O_INTERFACE_CONTROL__tbimode 27 88 #define O_INTERFACE_CONTROL__ghdmode 26 89 #define O_INTERFACE_CONTROL__lhdmode 25 90 #define O_INTERFACE_CONTROL__phymod 24 91 #define O_INTERFACE_CONTROL__hrrmi 23 92 #define O_INTERFACE_CONTROL__rspd 16 93 #define O_INTERFACE_CONTROL__hr100 15 94 #define O_INTERFACE_CONTROL__frcq 10 95 #define O_INTERFACE_CONTROL__nocfr 9 96 #define O_INTERFACE_CONTROL__dlfct 8 97 #define O_INTERFACE_CONTROL__enjab 0 98 #define R_INTERFACE_STATUS 0x0F 99 #define O_INTERFACE_STATUS__xsdfr 9 100 #define O_INTERFACE_STATUS__ssrr 8 101 #define W_INTERFACE_STATUS__ssrr 5 102 #define O_INTERFACE_STATUS__miilf 3 103 #define O_INTERFACE_STATUS__locar 2 104 #define O_INTERFACE_STATUS__sqerr 1 105 #define O_INTERFACE_STATUS__jabber 0 106 #define R_STATION_ADDRESS_LS 0x10 107 #define R_STATION_ADDRESS_MS 0x11 108 109 /* A-XGMAC register and bit field definitions */ 110 #define R_XGMAC_CONFIG_0 0x00 111 #define O_XGMAC_CONFIG_0__hstmacrst 31 112 #define O_XGMAC_CONFIG_0__hstrstrctl 23 113 #define O_XGMAC_CONFIG_0__hstrstrfn 22 114 #define O_XGMAC_CONFIG_0__hstrsttctl 18 115 #define O_XGMAC_CONFIG_0__hstrsttfn 17 116 #define O_XGMAC_CONFIG_0__hstrstmiim 16 117 #define O_XGMAC_CONFIG_0__hstloopback 8 118 #define R_XGMAC_CONFIG_1 0x01 119 #define O_XGMAC_CONFIG_1__hsttctlen 31 120 #define O_XGMAC_CONFIG_1__hsttfen 30 121 #define O_XGMAC_CONFIG_1__hstrctlen 29 122 #define O_XGMAC_CONFIG_1__hstrfen 28 123 #define O_XGMAC_CONFIG_1__tfen 26 124 #define O_XGMAC_CONFIG_1__rfen 24 125 #define O_XGMAC_CONFIG_1__hstrctlshrtp 12 126 #define O_XGMAC_CONFIG_1__hstdlyfcstx 10 127 #define W_XGMAC_CONFIG_1__hstdlyfcstx 2 128 #define O_XGMAC_CONFIG_1__hstdlyfcsrx 8 129 #define W_XGMAC_CONFIG_1__hstdlyfcsrx 2 130 #define O_XGMAC_CONFIG_1__hstppen 7 131 #define O_XGMAC_CONFIG_1__hstbytswp 6 132 #define O_XGMAC_CONFIG_1__hstdrplt64 5 133 #define O_XGMAC_CONFIG_1__hstprmscrx 4 134 #define O_XGMAC_CONFIG_1__hstlenchk 3 135 #define O_XGMAC_CONFIG_1__hstgenfcs 2 136 #define O_XGMAC_CONFIG_1__hstpadmode 0 137 #define W_XGMAC_CONFIG_1__hstpadmode 2 138 #define R_XGMAC_CONFIG_2 0x02 139 #define O_XGMAC_CONFIG_2__hsttctlfrcp 31 140 #define O_XGMAC_CONFIG_2__hstmlnkflth 27 141 #define O_XGMAC_CONFIG_2__hstalnkflth 26 142 #define O_XGMAC_CONFIG_2__rflnkflt 24 143 #define W_XGMAC_CONFIG_2__rflnkflt 2 144 #define O_XGMAC_CONFIG_2__hstipgextmod 16 145 #define W_XGMAC_CONFIG_2__hstipgextmod 5 146 #define O_XGMAC_CONFIG_2__hstrctlfrcp 15 147 #define O_XGMAC_CONFIG_2__hstipgexten 5 148 #define O_XGMAC_CONFIG_2__hstmipgext 0 149 #define W_XGMAC_CONFIG_2__hstmipgext 5 150 #define R_XGMAC_CONFIG_3 0x03 151 #define O_XGMAC_CONFIG_3__hstfltrfrm 31 152 #define W_XGMAC_CONFIG_3__hstfltrfrm 16 153 #define O_XGMAC_CONFIG_3__hstfltrfrmdc 15 154 #define W_XGMAC_CONFIG_3__hstfltrfrmdc 16 155 #define R_XGMAC_STATION_ADDRESS_LS 0x04 156 #define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0 157 #define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32 158 #define R_XGMAC_STATION_ADDRESS_MS 0x05 159 #define R_XGMAC_MAX_FRAME_LEN 0x08 160 #define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16 161 #define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14 162 #define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0 163 #define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16 164 #define R_XGMAC_REV_LEVEL 0x0B 165 #define O_XGMAC_REV_LEVEL__revlvl 0 166 #define W_XGMAC_REV_LEVEL__revlvl 15 167 #define R_XGMAC_MIIM_COMMAND 0x10 168 #define O_XGMAC_MIIM_COMMAND__hstldcmd 3 169 #define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0 170 #define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3 171 #define R_XGMAC_MIIM_FILED 0x11 172 #define O_XGMAC_MIIM_FILED__hststfield 30 173 #define W_XGMAC_MIIM_FILED__hststfield 2 174 #define O_XGMAC_MIIM_FILED__hstopfield 28 175 #define W_XGMAC_MIIM_FILED__hstopfield 2 176 #define O_XGMAC_MIIM_FILED__hstphyadx 23 177 #define W_XGMAC_MIIM_FILED__hstphyadx 5 178 #define O_XGMAC_MIIM_FILED__hstregadx 18 179 #define W_XGMAC_MIIM_FILED__hstregadx 5 180 #define O_XGMAC_MIIM_FILED__hsttafield 16 181 #define W_XGMAC_MIIM_FILED__hsttafield 2 182 #define O_XGMAC_MIIM_FILED__miimrddat 0 183 #define W_XGMAC_MIIM_FILED__miimrddat 16 184 #define R_XGMAC_MIIM_CONFIG 0x12 185 #define O_XGMAC_MIIM_CONFIG__hstnopram 7 186 #define O_XGMAC_MIIM_CONFIG__hstclkdiv 0 187 #define W_XGMAC_MIIM_CONFIG__hstclkdiv 7 188 #define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13 189 #define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0 190 #define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32 191 #define R_XGMAC_MIIM_INDICATOR 0x14 192 #define O_XGMAC_MIIM_INDICATOR__miimphylf 4 193 #define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3 194 #define O_XGMAC_MIIM_INDICATOR__miimmonvld 2 195 #define O_XGMAC_MIIM_INDICATOR__miimmon 1 196 #define O_XGMAC_MIIM_INDICATOR__miimbusy 0 197 198 /* GMAC stats registers */ 199 #define R_RBYT 0x27 200 #define R_RPKT 0x28 201 #define R_RFCS 0x29 202 #define R_RMCA 0x2A 203 #define R_RBCA 0x2B 204 #define R_RXCF 0x2C 205 #define R_RXPF 0x2D 206 #define R_RXUO 0x2E 207 #define R_RALN 0x2F 208 #define R_RFLR 0x30 209 #define R_RCDE 0x31 210 #define R_RCSE 0x32 211 #define R_RUND 0x33 212 #define R_ROVR 0x34 213 #define R_TBYT 0x38 214 #define R_TPKT 0x39 215 #define R_TMCA 0x3A 216 #define R_TBCA 0x3B 217 #define R_TXPF 0x3C 218 #define R_TDFR 0x3D 219 #define R_TEDF 0x3E 220 #define R_TSCL 0x3F 221 #define R_TMCL 0x40 222 #define R_TLCL 0x41 223 #define R_TXCL 0x42 224 #define R_TNCL 0x43 225 #define R_TJBR 0x46 226 #define R_TFCS 0x47 227 #define R_TXCF 0x48 228 #define R_TOVR 0x49 229 #define R_TUND 0x4A 230 #define R_TFRG 0x4B 231 232 /* Glue logic register and bit field definitions */ 233 #define R_MAC_ADDR0 0x50 234 #define R_MAC_ADDR1 0x52 235 #define R_MAC_ADDR2 0x54 236 #define R_MAC_ADDR3 0x56 237 #define R_MAC_ADDR_MASK2 0x58 238 #define R_MAC_ADDR_MASK3 0x5A 239 #define R_MAC_FILTER_CONFIG 0x5C 240 #define O_MAC_FILTER_CONFIG__BROADCAST_EN 10 241 #define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9 242 #define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8 243 #define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7 244 #define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6 245 #define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5 246 #define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4 247 #define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3 248 #define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2 249 #define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1 250 #define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0 251 #define R_HASH_TABLE_VECTOR 0x30 252 #define R_TX_CONTROL 0x0A0 253 #define O_TX_CONTROL__TX15HALT 31 254 #define O_TX_CONTROL__TX14HALT 30 255 #define O_TX_CONTROL__TX13HALT 29 256 #define O_TX_CONTROL__TX12HALT 28 257 #define O_TX_CONTROL__TX11HALT 27 258 #define O_TX_CONTROL__TX10HALT 26 259 #define O_TX_CONTROL__TX9HALT 25 260 #define O_TX_CONTROL__TX8HALT 24 261 #define O_TX_CONTROL__TX7HALT 23 262 #define O_TX_CONTROL__TX6HALT 22 263 #define O_TX_CONTROL__TX5HALT 21 264 #define O_TX_CONTROL__TX4HALT 20 265 #define O_TX_CONTROL__TX3HALT 19 266 #define O_TX_CONTROL__TX2HALT 18 267 #define O_TX_CONTROL__TX1HALT 17 268 #define O_TX_CONTROL__TX0HALT 16 269 #define O_TX_CONTROL__TXIDLE 15 270 #define O_TX_CONTROL__TXENABLE 14 271 #define O_TX_CONTROL__TXTHRESHOLD 0 272 #define W_TX_CONTROL__TXTHRESHOLD 14 273 #define R_RX_CONTROL 0x0A1 274 #define O_RX_CONTROL__RGMII 10 275 #define O_RX_CONTROL__SOFTRESET 2 276 #define O_RX_CONTROL__RXHALT 1 277 #define O_RX_CONTROL__RXENABLE 0 278 #define R_DESC_PACK_CTRL 0x0A2 279 #define O_DESC_PACK_CTRL__BYTEOFFSET 17 280 #define W_DESC_PACK_CTRL__BYTEOFFSET 3 281 #define O_DESC_PACK_CTRL__PREPADENABLE 16 282 #define O_DESC_PACK_CTRL__MAXENTRY 14 283 #define W_DESC_PACK_CTRL__MAXENTRY 2 284 #define O_DESC_PACK_CTRL__REGULARSIZE 0 285 #define W_DESC_PACK_CTRL__REGULARSIZE 14 286 #define R_STATCTRL 0x0A3 287 #define O_STATCTRL__OVERFLOWEN 4 288 #define O_STATCTRL__GIG 3 289 #define O_STATCTRL__STEN 2 290 #define O_STATCTRL__CLRCNT 1 291 #define O_STATCTRL__AUTOZ 0 292 #define R_L2ALLOCCTRL 0x0A4 293 #define O_L2ALLOCCTRL__TXL2ALLOCATE 9 294 #define W_L2ALLOCCTRL__TXL2ALLOCATE 9 295 #define O_L2ALLOCCTRL__RXL2ALLOCATE 0 296 #define W_L2ALLOCCTRL__RXL2ALLOCATE 9 297 #define R_INTMASK 0x0A5 298 #define O_INTMASK__SPI4TXERROR 28 299 #define O_INTMASK__SPI4RXERROR 27 300 #define O_INTMASK__RGMIIHALFDUPCOLLISION 27 301 #define O_INTMASK__ABORT 26 302 #define O_INTMASK__UNDERRUN 25 303 #define O_INTMASK__DISCARDPACKET 24 304 #define O_INTMASK__ASYNCFIFOFULL 23 305 #define O_INTMASK__TAGFULL 22 306 #define O_INTMASK__CLASS3FULL 21 307 #define O_INTMASK__C3EARLYFULL 20 308 #define O_INTMASK__CLASS2FULL 19 309 #define O_INTMASK__C2EARLYFULL 18 310 #define O_INTMASK__CLASS1FULL 17 311 #define O_INTMASK__C1EARLYFULL 16 312 #define O_INTMASK__CLASS0FULL 15 313 #define O_INTMASK__C0EARLYFULL 14 314 #define O_INTMASK__RXDATAFULL 13 315 #define O_INTMASK__RXEARLYFULL 12 316 #define O_INTMASK__RFREEEMPTY 9 317 #define O_INTMASK__RFEARLYEMPTY 8 318 #define O_INTMASK__P2PSPILLECC 7 319 #define O_INTMASK__FREEDESCFULL 5 320 #define O_INTMASK__FREEEARLYFULL 4 321 #define O_INTMASK__TXFETCHERROR 3 322 #define O_INTMASK__STATCARRY 2 323 #define O_INTMASK__MDINT 1 324 #define O_INTMASK__TXILLEGAL 0 325 #define R_INTREG 0x0A6 326 #define O_INTREG__SPI4TXERROR 28 327 #define O_INTREG__SPI4RXERROR 27 328 #define O_INTREG__RGMIIHALFDUPCOLLISION 27 329 #define O_INTREG__ABORT 26 330 #define O_INTREG__UNDERRUN 25 331 #define O_INTREG__DISCARDPACKET 24 332 #define O_INTREG__ASYNCFIFOFULL 23 333 #define O_INTREG__TAGFULL 22 334 #define O_INTREG__CLASS3FULL 21 335 #define O_INTREG__C3EARLYFULL 20 336 #define O_INTREG__CLASS2FULL 19 337 #define O_INTREG__C2EARLYFULL 18 338 #define O_INTREG__CLASS1FULL 17 339 #define O_INTREG__C1EARLYFULL 16 340 #define O_INTREG__CLASS0FULL 15 341 #define O_INTREG__C0EARLYFULL 14 342 #define O_INTREG__RXDATAFULL 13 343 #define O_INTREG__RXEARLYFULL 12 344 #define O_INTREG__RFREEEMPTY 9 345 #define O_INTREG__RFEARLYEMPTY 8 346 #define O_INTREG__P2PSPILLECC 7 347 #define O_INTREG__FREEDESCFULL 5 348 #define O_INTREG__FREEEARLYFULL 4 349 #define O_INTREG__TXFETCHERROR 3 350 #define O_INTREG__STATCARRY 2 351 #define O_INTREG__MDINT 1 352 #define O_INTREG__TXILLEGAL 0 353 #define R_TXRETRY 0x0A7 354 #define O_TXRETRY__COLLISIONRETRY 6 355 #define O_TXRETRY__BUSERRORRETRY 5 356 #define O_TXRETRY__UNDERRUNRETRY 4 357 #define O_TXRETRY__RETRIES 0 358 #define W_TXRETRY__RETRIES 4 359 #define R_CORECONTROL 0x0A8 360 #define O_CORECONTROL__ERRORTHREAD 4 361 #define W_CORECONTROL__ERRORTHREAD 7 362 #define O_CORECONTROL__SHUTDOWN 2 363 #define O_CORECONTROL__SPEED 0 364 #define W_CORECONTROL__SPEED 2 365 #define R_BYTEOFFSET0 0x0A9 366 #define R_BYTEOFFSET1 0x0AA 367 #define R_L2TYPE_0 0x0F0 368 #define O_L2TYPE__EXTRAHDRPROTOSIZE 26 369 #define W_L2TYPE__EXTRAHDRPROTOSIZE 5 370 #define O_L2TYPE__EXTRAHDRPROTOOFFSET 20 371 #define W_L2TYPE__EXTRAHDRPROTOOFFSET 6 372 #define O_L2TYPE__EXTRAHEADERSIZE 14 373 #define W_L2TYPE__EXTRAHEADERSIZE 6 374 #define O_L2TYPE__PROTOOFFSET 8 375 #define W_L2TYPE__PROTOOFFSET 6 376 #define O_L2TYPE__L2HDROFFSET 2 377 #define W_L2TYPE__L2HDROFFSET 6 378 #define O_L2TYPE__L2PROTO 0 379 #define W_L2TYPE__L2PROTO 2 380 #define R_L2TYPE_1 0xF0 381 #define R_L2TYPE_2 0xF0 382 #define R_L2TYPE_3 0xF0 383 #define R_PARSERCONFIGREG 0x100 384 #define O_PARSERCONFIGREG__CRCHASHPOLY 8 385 #define W_PARSERCONFIGREG__CRCHASHPOLY 7 386 #define O_PARSERCONFIGREG__PREPADOFFSET 4 387 #define W_PARSERCONFIGREG__PREPADOFFSET 4 388 #define O_PARSERCONFIGREG__USECAM 2 389 #define O_PARSERCONFIGREG__USEHASH 1 390 #define O_PARSERCONFIGREG__USEPROTO 0 391 #define R_L3CTABLE 0x140 392 #define O_L3CTABLE__OFFSET0 25 393 #define W_L3CTABLE__OFFSET0 7 394 #define O_L3CTABLE__LEN0 21 395 #define W_L3CTABLE__LEN0 4 396 #define O_L3CTABLE__OFFSET1 14 397 #define W_L3CTABLE__OFFSET1 7 398 #define O_L3CTABLE__LEN1 10 399 #define W_L3CTABLE__LEN1 4 400 #define O_L3CTABLE__OFFSET2 4 401 #define W_L3CTABLE__OFFSET2 6 402 #define O_L3CTABLE__LEN2 0 403 #define W_L3CTABLE__LEN2 4 404 #define O_L3CTABLE__L3HDROFFSET 26 405 #define W_L3CTABLE__L3HDROFFSET 6 406 #define O_L3CTABLE__L4PROTOOFFSET 20 407 #define W_L3CTABLE__L4PROTOOFFSET 6 408 #define O_L3CTABLE__IPCHKSUMCOMPUTE 19 409 #define O_L3CTABLE__L4CLASSIFY 18 410 #define O_L3CTABLE__L2PROTO 16 411 #define W_L3CTABLE__L2PROTO 2 412 #define O_L3CTABLE__L3PROTOKEY 0 413 #define W_L3CTABLE__L3PROTOKEY 16 414 #define R_L4CTABLE 0x160 415 #define O_L4CTABLE__OFFSET0 21 416 #define W_L4CTABLE__OFFSET0 6 417 #define O_L4CTABLE__LEN0 17 418 #define W_L4CTABLE__LEN0 4 419 #define O_L4CTABLE__OFFSET1 11 420 #define W_L4CTABLE__OFFSET1 6 421 #define O_L4CTABLE__LEN1 7 422 #define W_L4CTABLE__LEN1 4 423 #define O_L4CTABLE__TCPCHKSUMENABLE 0 424 #define R_CAM4X128TABLE 0x172 425 #define O_CAM4X128TABLE__CLASSID 7 426 #define W_CAM4X128TABLE__CLASSID 2 427 #define O_CAM4X128TABLE__BUCKETID 1 428 #define W_CAM4X128TABLE__BUCKETID 6 429 #define O_CAM4X128TABLE__USEBUCKET 0 430 #define R_CAM4X128KEY 0x180 431 #define R_TRANSLATETABLE 0x1A0 432 #define R_DMACR0 0x200 433 #define O_DMACR0__DATA0WRMAXCR 27 434 #define W_DMACR0__DATA0WRMAXCR 3 435 #define O_DMACR0__DATA0RDMAXCR 24 436 #define W_DMACR0__DATA0RDMAXCR 3 437 #define O_DMACR0__DATA1WRMAXCR 21 438 #define W_DMACR0__DATA1WRMAXCR 3 439 #define O_DMACR0__DATA1RDMAXCR 18 440 #define W_DMACR0__DATA1RDMAXCR 3 441 #define O_DMACR0__DATA2WRMAXCR 15 442 #define W_DMACR0__DATA2WRMAXCR 3 443 #define O_DMACR0__DATA2RDMAXCR 12 444 #define W_DMACR0__DATA2RDMAXCR 3 445 #define O_DMACR0__DATA3WRMAXCR 9 446 #define W_DMACR0__DATA3WRMAXCR 3 447 #define O_DMACR0__DATA3RDMAXCR 6 448 #define W_DMACR0__DATA3RDMAXCR 3 449 #define O_DMACR0__DATA4WRMAXCR 3 450 #define W_DMACR0__DATA4WRMAXCR 3 451 #define O_DMACR0__DATA4RDMAXCR 0 452 #define W_DMACR0__DATA4RDMAXCR 3 453 #define R_DMACR1 0x201 454 #define O_DMACR1__DATA5WRMAXCR 27 455 #define W_DMACR1__DATA5WRMAXCR 3 456 #define O_DMACR1__DATA5RDMAXCR 24 457 #define W_DMACR1__DATA5RDMAXCR 3 458 #define O_DMACR1__DATA6WRMAXCR 21 459 #define W_DMACR1__DATA6WRMAXCR 3 460 #define O_DMACR1__DATA6RDMAXCR 18 461 #define W_DMACR1__DATA6RDMAXCR 3 462 #define O_DMACR1__DATA7WRMAXCR 15 463 #define W_DMACR1__DATA7WRMAXCR 3 464 #define O_DMACR1__DATA7RDMAXCR 12 465 #define W_DMACR1__DATA7RDMAXCR 3 466 #define O_DMACR1__DATA8WRMAXCR 9 467 #define W_DMACR1__DATA8WRMAXCR 3 468 #define O_DMACR1__DATA8RDMAXCR 6 469 #define W_DMACR1__DATA8RDMAXCR 3 470 #define O_DMACR1__DATA9WRMAXCR 3 471 #define W_DMACR1__DATA9WRMAXCR 3 472 #define O_DMACR1__DATA9RDMAXCR 0 473 #define W_DMACR1__DATA9RDMAXCR 3 474 #define R_DMACR2 0x202 475 #define O_DMACR2__DATA10WRMAXCR 27 476 #define W_DMACR2__DATA10WRMAXCR 3 477 #define O_DMACR2__DATA10RDMAXCR 24 478 #define W_DMACR2__DATA10RDMAXCR 3 479 #define O_DMACR2__DATA11WRMAXCR 21 480 #define W_DMACR2__DATA11WRMAXCR 3 481 #define O_DMACR2__DATA11RDMAXCR 18 482 #define W_DMACR2__DATA11RDMAXCR 3 483 #define O_DMACR2__DATA12WRMAXCR 15 484 #define W_DMACR2__DATA12WRMAXCR 3 485 #define O_DMACR2__DATA12RDMAXCR 12 486 #define W_DMACR2__DATA12RDMAXCR 3 487 #define O_DMACR2__DATA13WRMAXCR 9 488 #define W_DMACR2__DATA13WRMAXCR 3 489 #define O_DMACR2__DATA13RDMAXCR 6 490 #define W_DMACR2__DATA13RDMAXCR 3 491 #define O_DMACR2__DATA14WRMAXCR 3 492 #define W_DMACR2__DATA14WRMAXCR 3 493 #define O_DMACR2__DATA14RDMAXCR 0 494 #define W_DMACR2__DATA14RDMAXCR 3 495 #define R_DMACR3 0x203 496 #define O_DMACR3__DATA15WRMAXCR 27 497 #define W_DMACR3__DATA15WRMAXCR 3 498 #define O_DMACR3__DATA15RDMAXCR 24 499 #define W_DMACR3__DATA15RDMAXCR 3 500 #define O_DMACR3__SPCLASSWRMAXCR 21 501 #define W_DMACR3__SPCLASSWRMAXCR 3 502 #define O_DMACR3__SPCLASSRDMAXCR 18 503 #define W_DMACR3__SPCLASSRDMAXCR 3 504 #define O_DMACR3__JUMFRINWRMAXCR 15 505 #define W_DMACR3__JUMFRINWRMAXCR 3 506 #define O_DMACR3__JUMFRINRDMAXCR 12 507 #define W_DMACR3__JUMFRINRDMAXCR 3 508 #define O_DMACR3__REGFRINWRMAXCR 9 509 #define W_DMACR3__REGFRINWRMAXCR 3 510 #define O_DMACR3__REGFRINRDMAXCR 6 511 #define W_DMACR3__REGFRINRDMAXCR 3 512 #define O_DMACR3__FROUTWRMAXCR 3 513 #define W_DMACR3__FROUTWRMAXCR 3 514 #define O_DMACR3__FROUTRDMAXCR 0 515 #define W_DMACR3__FROUTRDMAXCR 3 516 #define R_REG_FRIN_SPILL_MEM_START_0 0x204 517 #define O_REG_FRIN_SPILL_MEM_START_0__REGFRINSPILLMEMSTART0 0 518 #define W_REG_FRIN_SPILL_MEM_START_0__REGFRINSPILLMEMSTART0 32 519 #define R_REG_FRIN_SPILL_MEM_START_1 0x205 520 #define O_REG_FRIN_SPILL_MEM_START_1__REGFRINSPILLMEMSTART1 0 521 #define W_REG_FRIN_SPILL_MEM_START_1__REGFRINSPILLMEMSTART1 3 522 #define R_REG_FRIN_SPILL_MEM_SIZE 0x206 523 #define O_REG_FRIN_SPILL_MEM_SIZE__REGFRINSPILLMEMSIZE 0 524 #define W_REG_FRIN_SPILL_MEM_SIZE__REGFRINSPILLMEMSIZE 32 525 #define R_FROUT_SPILL_MEM_START_0 0x207 526 #define O_FROUT_SPILL_MEM_START_0__FROUTSPILLMEMSTART0 0 527 #define W_FROUT_SPILL_MEM_START_0__FROUTSPILLMEMSTART0 32 528 #define R_FROUT_SPILL_MEM_START_1 0x208 529 #define O_FROUT_SPILL_MEM_START_1__FROUTSPILLMEMSTART1 0 530 #define W_FROUT_SPILL_MEM_START_1__FROUTSPILLMEMSTART1 3 531 #define R_FROUT_SPILL_MEM_SIZE 0x209 532 #define O_FROUT_SPILL_MEM_SIZE__FROUTSPILLMEMSIZE 0 533 #define W_FROUT_SPILL_MEM_SIZE__FROUTSPILLMEMSIZE 32 534 #define R_CLASS0_SPILL_MEM_START_0 0x20A 535 #define O_CLASS0_SPILL_MEM_START_0__CLASS0SPILLMEMSTART0 0 536 #define W_CLASS0_SPILL_MEM_START_0__CLASS0SPILLMEMSTART0 32 537 #define R_CLASS0_SPILL_MEM_START_1 0x20B 538 #define O_CLASS0_SPILL_MEM_START_1__CLASS0SPILLMEMSTART1 0 539 #define W_CLASS0_SPILL_MEM_START_1__CLASS0SPILLMEMSTART1 3 540 #define R_CLASS0_SPILL_MEM_SIZE 0x20C 541 #define O_CLASS0_SPILL_MEM_SIZE__CLASS0SPILLMEMSIZE 0 542 #define W_CLASS0_SPILL_MEM_SIZE__CLASS0SPILLMEMSIZE 32 543 #define R_JUMFRIN_SPILL_MEM_START_0 0x20D 544 #define O_JUMFRIN_SPILL_MEM_START_0__JUMFRINSPILLMEMSTART0 0 545 #define W_JUMFRIN_SPILL_MEM_START_0__JUMFRINSPILLMEMSTART0 32 546 #define R_JUMFRIN_SPILL_MEM_START_1 0x20E 547 #define O_JUMFRIN_SPILL_MEM_START_1__JUMFRINSPILLMEMSTART1 0 548 #define W_JUMFRIN_SPILL_MEM_START_1__JUMFRINSPILLMEMSTART1 3 549 #define R_JUMFRIN_SPILL_MEM_SIZE 0x20F 550 #define O_JUMFRIN_SPILL_MEM_SIZE__JUMFRINSPILLMEMSIZE 0 551 #define W_JUMFRIN_SPILL_MEM_SIZE__JUMFRINSPILLMEMSIZE 32 552 #define R_CLASS1_SPILL_MEM_START_0 0x210 553 #define O_CLASS1_SPILL_MEM_START_0__CLASS1SPILLMEMSTART0 0 554 #define W_CLASS1_SPILL_MEM_START_0__CLASS1SPILLMEMSTART0 32 555 #define R_CLASS1_SPILL_MEM_START_1 0x211 556 #define O_CLASS1_SPILL_MEM_START_1__CLASS1SPILLMEMSTART1 0 557 #define W_CLASS1_SPILL_MEM_START_1__CLASS1SPILLMEMSTART1 3 558 #define R_CLASS1_SPILL_MEM_SIZE 0x212 559 #define O_CLASS1_SPILL_MEM_SIZE__CLASS1SPILLMEMSIZE 0 560 #define W_CLASS1_SPILL_MEM_SIZE__CLASS1SPILLMEMSIZE 32 561 #define R_CLASS2_SPILL_MEM_START_0 0x213 562 #define O_CLASS2_SPILL_MEM_START_0__CLASS2SPILLMEMSTART0 0 563 #define W_CLASS2_SPILL_MEM_START_0__CLASS2SPILLMEMSTART0 32 564 #define R_CLASS2_SPILL_MEM_START_1 0x214 565 #define O_CLASS2_SPILL_MEM_START_1__CLASS2SPILLMEMSTART1 0 566 #define W_CLASS2_SPILL_MEM_START_1__CLASS2SPILLMEMSTART1 3 567 #define R_CLASS2_SPILL_MEM_SIZE 0x215 568 #define O_CLASS2_SPILL_MEM_SIZE__CLASS2SPILLMEMSIZE 0 569 #define W_CLASS2_SPILL_MEM_SIZE__CLASS2SPILLMEMSIZE 32 570 #define R_CLASS3_SPILL_MEM_START_0 0x216 571 #define O_CLASS3_SPILL_MEM_START_0__CLASS3SPILLMEMSTART0 0 572 #define W_CLASS3_SPILL_MEM_START_0__CLASS3SPILLMEMSTART0 32 573 #define R_CLASS3_SPILL_MEM_START_1 0x217 574 #define O_CLASS3_SPILL_MEM_START_1__CLASS3SPILLMEMSTART1 0 575 #define W_CLASS3_SPILL_MEM_START_1__CLASS3SPILLMEMSTART1 3 576 #define R_CLASS3_SPILL_MEM_SIZE 0x218 577 #define O_CLASS3_SPILL_MEM_SIZE__CLASS3SPILLMEMSIZE 0 578 #define W_CLASS3_SPILL_MEM_SIZE__CLASS3SPILLMEMSIZE 32 579 #define R_REG_FRIN1_SPILL_MEM_START_0 0x219 580 #define R_REG_FRIN1_SPILL_MEM_START_1 0x21a 581 #define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b 582 #define R_SPIHNGY0 0x219 583 #define O_SPIHNGY0__EG_HNGY_THRESH_0 24 584 #define W_SPIHNGY0__EG_HNGY_THRESH_0 7 585 #define O_SPIHNGY0__EG_HNGY_THRESH_1 16 586 #define W_SPIHNGY0__EG_HNGY_THRESH_1 7 587 #define O_SPIHNGY0__EG_HNGY_THRESH_2 8 588 #define W_SPIHNGY0__EG_HNGY_THRESH_2 7 589 #define O_SPIHNGY0__EG_HNGY_THRESH_3 0 590 #define W_SPIHNGY0__EG_HNGY_THRESH_3 7 591 #define R_SPIHNGY1 0x21A 592 #define O_SPIHNGY1__EG_HNGY_THRESH_4 24 593 #define W_SPIHNGY1__EG_HNGY_THRESH_4 7 594 #define O_SPIHNGY1__EG_HNGY_THRESH_5 16 595 #define W_SPIHNGY1__EG_HNGY_THRESH_5 7 596 #define O_SPIHNGY1__EG_HNGY_THRESH_6 8 597 #define W_SPIHNGY1__EG_HNGY_THRESH_6 7 598 #define O_SPIHNGY1__EG_HNGY_THRESH_7 0 599 #define W_SPIHNGY1__EG_HNGY_THRESH_7 7 600 #define R_SPIHNGY2 0x21B 601 #define O_SPIHNGY2__EG_HNGY_THRESH_8 24 602 #define W_SPIHNGY2__EG_HNGY_THRESH_8 7 603 #define O_SPIHNGY2__EG_HNGY_THRESH_9 16 604 #define W_SPIHNGY2__EG_HNGY_THRESH_9 7 605 #define O_SPIHNGY2__EG_HNGY_THRESH_10 8 606 #define W_SPIHNGY2__EG_HNGY_THRESH_10 7 607 #define O_SPIHNGY2__EG_HNGY_THRESH_11 0 608 #define W_SPIHNGY2__EG_HNGY_THRESH_11 7 609 #define R_SPIHNGY3 0x21C 610 #define O_SPIHNGY3__EG_HNGY_THRESH_12 24 611 #define W_SPIHNGY3__EG_HNGY_THRESH_12 7 612 #define O_SPIHNGY3__EG_HNGY_THRESH_13 16 613 #define W_SPIHNGY3__EG_HNGY_THRESH_13 7 614 #define O_SPIHNGY3__EG_HNGY_THRESH_14 8 615 #define W_SPIHNGY3__EG_HNGY_THRESH_14 7 616 #define O_SPIHNGY3__EG_HNGY_THRESH_15 0 617 #define W_SPIHNGY3__EG_HNGY_THRESH_15 7 618 #define R_SPISTRV0 0x21D 619 #define O_SPISTRV0__EG_STRV_THRESH_0 24 620 #define W_SPISTRV0__EG_STRV_THRESH_0 7 621 #define O_SPISTRV0__EG_STRV_THRESH_1 16 622 #define W_SPISTRV0__EG_STRV_THRESH_1 7 623 #define O_SPISTRV0__EG_STRV_THRESH_2 8 624 #define W_SPISTRV0__EG_STRV_THRESH_2 7 625 #define O_SPISTRV0__EG_STRV_THRESH_3 0 626 #define W_SPISTRV0__EG_STRV_THRESH_3 7 627 #define R_SPISTRV1 0x21E 628 #define O_SPISTRV1__EG_STRV_THRESH_4 24 629 #define W_SPISTRV1__EG_STRV_THRESH_4 7 630 #define O_SPISTRV1__EG_STRV_THRESH_5 16 631 #define W_SPISTRV1__EG_STRV_THRESH_5 7 632 #define O_SPISTRV1__EG_STRV_THRESH_6 8 633 #define W_SPISTRV1__EG_STRV_THRESH_6 7 634 #define O_SPISTRV1__EG_STRV_THRESH_7 0 635 #define W_SPISTRV1__EG_STRV_THRESH_7 7 636 #define R_SPISTRV2 0x21F 637 #define O_SPISTRV2__EG_STRV_THRESH_8 24 638 #define W_SPISTRV2__EG_STRV_THRESH_8 7 639 #define O_SPISTRV2__EG_STRV_THRESH_9 16 640 #define W_SPISTRV2__EG_STRV_THRESH_9 7 641 #define O_SPISTRV2__EG_STRV_THRESH_10 8 642 #define W_SPISTRV2__EG_STRV_THRESH_10 7 643 #define O_SPISTRV2__EG_STRV_THRESH_11 0 644 #define W_SPISTRV2__EG_STRV_THRESH_11 7 645 #define R_SPISTRV3 0x220 646 #define O_SPISTRV3__EG_STRV_THRESH_12 24 647 #define W_SPISTRV3__EG_STRV_THRESH_12 7 648 #define O_SPISTRV3__EG_STRV_THRESH_13 16 649 #define W_SPISTRV3__EG_STRV_THRESH_13 7 650 #define O_SPISTRV3__EG_STRV_THRESH_14 8 651 #define W_SPISTRV3__EG_STRV_THRESH_14 7 652 #define O_SPISTRV3__EG_STRV_THRESH_15 0 653 #define W_SPISTRV3__EG_STRV_THRESH_15 7 654 #define R_TXDATAFIFO0 0x221 655 #define O_TXDATAFIFO0__TX0DATAFIFOSTART 24 656 #define W_TXDATAFIFO0__TX0DATAFIFOSTART 7 657 #define O_TXDATAFIFO0__TX0DATAFIFOSIZE 16 658 #define W_TXDATAFIFO0__TX0DATAFIFOSIZE 7 659 #define O_TXDATAFIFO0__TX1DATAFIFOSTART 8 660 #define W_TXDATAFIFO0__TX1DATAFIFOSTART 7 661 #define O_TXDATAFIFO0__TX1DATAFIFOSIZE 0 662 #define W_TXDATAFIFO0__TX1DATAFIFOSIZE 7 663 #define R_TXDATAFIFO1 0x222 664 #define O_TXDATAFIFO1__TX2DATAFIFOSTART 24 665 #define W_TXDATAFIFO1__TX2DATAFIFOSTART 7 666 #define O_TXDATAFIFO1__TX2DATAFIFOSIZE 16 667 #define W_TXDATAFIFO1__TX2DATAFIFOSIZE 7 668 #define O_TXDATAFIFO1__TX3DATAFIFOSTART 8 669 #define W_TXDATAFIFO1__TX3DATAFIFOSTART 7 670 #define O_TXDATAFIFO1__TX3DATAFIFOSIZE 0 671 #define W_TXDATAFIFO1__TX3DATAFIFOSIZE 7 672 #define R_TXDATAFIFO2 0x223 673 #define O_TXDATAFIFO2__TX4DATAFIFOSTART 24 674 #define W_TXDATAFIFO2__TX4DATAFIFOSTART 7 675 #define O_TXDATAFIFO2__TX4DATAFIFOSIZE 16 676 #define W_TXDATAFIFO2__TX4DATAFIFOSIZE 7 677 #define O_TXDATAFIFO2__TX5DATAFIFOSTART 8 678 #define W_TXDATAFIFO2__TX5DATAFIFOSTART 7 679 #define O_TXDATAFIFO2__TX5DATAFIFOSIZE 0 680 #define W_TXDATAFIFO2__TX5DATAFIFOSIZE 7 681 #define R_TXDATAFIFO3 0x224 682 #define O_TXDATAFIFO3__TX6DATAFIFOSTART 24 683 #define W_TXDATAFIFO3__TX6DATAFIFOSTART 7 684 #define O_TXDATAFIFO3__TX6DATAFIFOSIZE 16 685 #define W_TXDATAFIFO3__TX6DATAFIFOSIZE 7 686 #define O_TXDATAFIFO3__TX7DATAFIFOSTART 8 687 #define W_TXDATAFIFO3__TX7DATAFIFOSTART 7 688 #define O_TXDATAFIFO3__TX7DATAFIFOSIZE 0 689 #define W_TXDATAFIFO3__TX7DATAFIFOSIZE 7 690 #define R_TXDATAFIFO4 0x225 691 #define O_TXDATAFIFO4__TX8DATAFIFOSTART 24 692 #define W_TXDATAFIFO4__TX8DATAFIFOSTART 7 693 #define O_TXDATAFIFO4__TX8DATAFIFOSIZE 16 694 #define W_TXDATAFIFO4__TX8DATAFIFOSIZE 7 695 #define O_TXDATAFIFO4__TX9DATAFIFOSTART 8 696 #define W_TXDATAFIFO4__TX9DATAFIFOSTART 7 697 #define O_TXDATAFIFO4__TX9DATAFIFOSIZE 0 698 #define W_TXDATAFIFO4__TX9DATAFIFOSIZE 7 699 #define R_TXDATAFIFO5 0x226 700 #define O_TXDATAFIFO5__TX10DATAFIFOSTART 24 701 #define W_TXDATAFIFO5__TX10DATAFIFOSTART 7 702 #define O_TXDATAFIFO5__TX10DATAFIFOSIZE 16 703 #define W_TXDATAFIFO5__TX10DATAFIFOSIZE 7 704 #define O_TXDATAFIFO5__TX11DATAFIFOSTART 8 705 #define W_TXDATAFIFO5__TX11DATAFIFOSTART 7 706 #define O_TXDATAFIFO5__TX11DATAFIFOSIZE 0 707 #define W_TXDATAFIFO5__TX11DATAFIFOSIZE 7 708 #define R_TXDATAFIFO6 0x227 709 #define O_TXDATAFIFO6__TX12DATAFIFOSTART 24 710 #define W_TXDATAFIFO6__TX12DATAFIFOSTART 7 711 #define O_TXDATAFIFO6__TX12DATAFIFOSIZE 16 712 #define W_TXDATAFIFO6__TX12DATAFIFOSIZE 7 713 #define O_TXDATAFIFO6__TX13DATAFIFOSTART 8 714 #define W_TXDATAFIFO6__TX13DATAFIFOSTART 7 715 #define O_TXDATAFIFO6__TX13DATAFIFOSIZE 0 716 #define W_TXDATAFIFO6__TX13DATAFIFOSIZE 7 717 #define R_TXDATAFIFO7 0x228 718 #define O_TXDATAFIFO7__TX14DATAFIFOSTART 24 719 #define W_TXDATAFIFO7__TX14DATAFIFOSTART 7 720 #define O_TXDATAFIFO7__TX14DATAFIFOSIZE 16 721 #define W_TXDATAFIFO7__TX14DATAFIFOSIZE 7 722 #define O_TXDATAFIFO7__TX15DATAFIFOSTART 8 723 #define W_TXDATAFIFO7__TX15DATAFIFOSTART 7 724 #define O_TXDATAFIFO7__TX15DATAFIFOSIZE 0 725 #define W_TXDATAFIFO7__TX15DATAFIFOSIZE 7 726 #define R_RXDATAFIFO0 0x229 727 #define O_RXDATAFIFO0__RX0DATAFIFOSTART 24 728 #define W_RXDATAFIFO0__RX0DATAFIFOSTART 7 729 #define O_RXDATAFIFO0__RX0DATAFIFOSIZE 16 730 #define W_RXDATAFIFO0__RX0DATAFIFOSIZE 7 731 #define O_RXDATAFIFO0__RX1DATAFIFOSTART 8 732 #define W_RXDATAFIFO0__RX1DATAFIFOSTART 7 733 #define O_RXDATAFIFO0__RX1DATAFIFOSIZE 0 734 #define W_RXDATAFIFO0__RX1DATAFIFOSIZE 7 735 #define R_RXDATAFIFO1 0x22A 736 #define O_RXDATAFIFO1__RX2DATAFIFOSTART 24 737 #define W_RXDATAFIFO1__RX2DATAFIFOSTART 7 738 #define O_RXDATAFIFO1__RX2DATAFIFOSIZE 16 739 #define W_RXDATAFIFO1__RX2DATAFIFOSIZE 7 740 #define O_RXDATAFIFO1__RX3DATAFIFOSTART 8 741 #define W_RXDATAFIFO1__RX3DATAFIFOSTART 7 742 #define O_RXDATAFIFO1__RX3DATAFIFOSIZE 0 743 #define W_RXDATAFIFO1__RX3DATAFIFOSIZE 7 744 #define R_RXDATAFIFO2 0x22B 745 #define O_RXDATAFIFO2__RX4DATAFIFOSTART 24 746 #define W_RXDATAFIFO2__RX4DATAFIFOSTART 7 747 #define O_RXDATAFIFO2__RX4DATAFIFOSIZE 16 748 #define W_RXDATAFIFO2__RX4DATAFIFOSIZE 7 749 #define O_RXDATAFIFO2__RX5DATAFIFOSTART 8 750 #define W_RXDATAFIFO2__RX5DATAFIFOSTART 7 751 #define O_RXDATAFIFO2__RX5DATAFIFOSIZE 0 752 #define W_RXDATAFIFO2__RX5DATAFIFOSIZE 7 753 #define R_RXDATAFIFO3 0x22C 754 #define O_RXDATAFIFO3__RX6DATAFIFOSTART 24 755 #define W_RXDATAFIFO3__RX6DATAFIFOSTART 7 756 #define O_RXDATAFIFO3__RX6DATAFIFOSIZE 16 757 #define W_RXDATAFIFO3__RX6DATAFIFOSIZE 7 758 #define O_RXDATAFIFO3__RX7DATAFIFOSTART 8 759 #define W_RXDATAFIFO3__RX7DATAFIFOSTART 7 760 #define O_RXDATAFIFO3__RX7DATAFIFOSIZE 0 761 #define W_RXDATAFIFO3__RX7DATAFIFOSIZE 7 762 #define R_RXDATAFIFO4 0x22D 763 #define O_RXDATAFIFO4__RX8DATAFIFOSTART 24 764 #define W_RXDATAFIFO4__RX8DATAFIFOSTART 7 765 #define O_RXDATAFIFO4__RX8DATAFIFOSIZE 16 766 #define W_RXDATAFIFO4__RX8DATAFIFOSIZE 7 767 #define O_RXDATAFIFO4__RX9DATAFIFOSTART 8 768 #define W_RXDATAFIFO4__RX9DATAFIFOSTART 7 769 #define O_RXDATAFIFO4__RX9DATAFIFOSIZE 0 770 #define W_RXDATAFIFO4__RX9DATAFIFOSIZE 7 771 #define R_RXDATAFIFO5 0x22E 772 #define O_RXDATAFIFO5__RX10DATAFIFOSTART 24 773 #define W_RXDATAFIFO5__RX10DATAFIFOSTART 7 774 #define O_RXDATAFIFO5__RX10DATAFIFOSIZE 16 775 #define W_RXDATAFIFO5__RX10DATAFIFOSIZE 7 776 #define O_RXDATAFIFO5__RX11DATAFIFOSTART 8 777 #define W_RXDATAFIFO5__RX11DATAFIFOSTART 7 778 #define O_RXDATAFIFO5__RX11DATAFIFOSIZE 0 779 #define W_RXDATAFIFO5__RX11DATAFIFOSIZE 7 780 #define R_RXDATAFIFO6 0x22F 781 #define O_RXDATAFIFO6__RX12DATAFIFOSTART 24 782 #define W_RXDATAFIFO6__RX12DATAFIFOSTART 7 783 #define O_RXDATAFIFO6__RX12DATAFIFOSIZE 16 784 #define W_RXDATAFIFO6__RX12DATAFIFOSIZE 7 785 #define O_RXDATAFIFO6__RX13DATAFIFOSTART 8 786 #define W_RXDATAFIFO6__RX13DATAFIFOSTART 7 787 #define O_RXDATAFIFO6__RX13DATAFIFOSIZE 0 788 #define W_RXDATAFIFO6__RX13DATAFIFOSIZE 7 789 #define R_RXDATAFIFO7 0x230 790 #define O_RXDATAFIFO7__RX14DATAFIFOSTART 24 791 #define W_RXDATAFIFO7__RX14DATAFIFOSTART 7 792 #define O_RXDATAFIFO7__RX14DATAFIFOSIZE 16 793 #define W_RXDATAFIFO7__RX14DATAFIFOSIZE 7 794 #define O_RXDATAFIFO7__RX15DATAFIFOSTART 8 795 #define W_RXDATAFIFO7__RX15DATAFIFOSTART 7 796 #define O_RXDATAFIFO7__RX15DATAFIFOSIZE 0 797 #define W_RXDATAFIFO7__RX15DATAFIFOSIZE 7 798 #define R_XGMACPADCALIBRATION 0x231 799 #define R_FREEQCARVE 0x233 800 #define R_SPI4STATICDELAY0 0x240 801 #define O_SPI4STATICDELAY0__DATALINE7 28 802 #define W_SPI4STATICDELAY0__DATALINE7 4 803 #define O_SPI4STATICDELAY0__DATALINE6 24 804 #define W_SPI4STATICDELAY0__DATALINE6 4 805 #define O_SPI4STATICDELAY0__DATALINE5 20 806 #define W_SPI4STATICDELAY0__DATALINE5 4 807 #define O_SPI4STATICDELAY0__DATALINE4 16 808 #define W_SPI4STATICDELAY0__DATALINE4 4 809 #define O_SPI4STATICDELAY0__DATALINE3 12 810 #define W_SPI4STATICDELAY0__DATALINE3 4 811 #define O_SPI4STATICDELAY0__DATALINE2 8 812 #define W_SPI4STATICDELAY0__DATALINE2 4 813 #define O_SPI4STATICDELAY0__DATALINE1 4 814 #define W_SPI4STATICDELAY0__DATALINE1 4 815 #define O_SPI4STATICDELAY0__DATALINE0 0 816 #define W_SPI4STATICDELAY0__DATALINE0 4 817 #define R_SPI4STATICDELAY1 0x241 818 #define O_SPI4STATICDELAY1__DATALINE15 28 819 #define W_SPI4STATICDELAY1__DATALINE15 4 820 #define O_SPI4STATICDELAY1__DATALINE14 24 821 #define W_SPI4STATICDELAY1__DATALINE14 4 822 #define O_SPI4STATICDELAY1__DATALINE13 20 823 #define W_SPI4STATICDELAY1__DATALINE13 4 824 #define O_SPI4STATICDELAY1__DATALINE12 16 825 #define W_SPI4STATICDELAY1__DATALINE12 4 826 #define O_SPI4STATICDELAY1__DATALINE11 12 827 #define W_SPI4STATICDELAY1__DATALINE11 4 828 #define O_SPI4STATICDELAY1__DATALINE10 8 829 #define W_SPI4STATICDELAY1__DATALINE10 4 830 #define O_SPI4STATICDELAY1__DATALINE9 4 831 #define W_SPI4STATICDELAY1__DATALINE9 4 832 #define O_SPI4STATICDELAY1__DATALINE8 0 833 #define W_SPI4STATICDELAY1__DATALINE8 4 834 #define R_SPI4STATICDELAY2 0x242 835 #define O_SPI4STATICDELAY0__TXSTAT1 8 836 #define W_SPI4STATICDELAY0__TXSTAT1 4 837 #define O_SPI4STATICDELAY0__TXSTAT0 4 838 #define W_SPI4STATICDELAY0__TXSTAT0 4 839 #define O_SPI4STATICDELAY0__RXCONTROL 0 840 #define W_SPI4STATICDELAY0__RXCONTROL 4 841 #define R_SPI4CONTROL 0x243 842 #define O_SPI4CONTROL__STATICDELAY 2 843 #define O_SPI4CONTROL__LVDS_LVTTL 1 844 #define O_SPI4CONTROL__SPI4ENABLE 0 845 #define R_CLASSWATERMARKS 0x244 846 #define O_CLASSWATERMARKS__CLASS0WATERMARK 24 847 #define W_CLASSWATERMARKS__CLASS0WATERMARK 5 848 #define O_CLASSWATERMARKS__CLASS1WATERMARK 16 849 #define W_CLASSWATERMARKS__CLASS1WATERMARK 5 850 #define O_CLASSWATERMARKS__CLASS3WATERMARK 0 851 #define W_CLASSWATERMARKS__CLASS3WATERMARK 5 852 #define R_RXWATERMARKS1 0x245 853 #define O_RXWATERMARKS__RX0DATAWATERMARK 24 854 #define W_RXWATERMARKS__RX0DATAWATERMARK 7 855 #define O_RXWATERMARKS__RX1DATAWATERMARK 16 856 #define W_RXWATERMARKS__RX1DATAWATERMARK 7 857 #define O_RXWATERMARKS__RX3DATAWATERMARK 0 858 #define W_RXWATERMARKS__RX3DATAWATERMARK 7 859 #define R_RXWATERMARKS2 0x246 860 #define O_RXWATERMARKS__RX4DATAWATERMARK 24 861 #define W_RXWATERMARKS__RX4DATAWATERMARK 7 862 #define O_RXWATERMARKS__RX5DATAWATERMARK 16 863 #define W_RXWATERMARKS__RX5DATAWATERMARK 7 864 #define O_RXWATERMARKS__RX6DATAWATERMARK 8 865 #define W_RXWATERMARKS__RX6DATAWATERMARK 7 866 #define O_RXWATERMARKS__RX7DATAWATERMARK 0 867 #define W_RXWATERMARKS__RX7DATAWATERMARK 7 868 #define R_RXWATERMARKS3 0x247 869 #define O_RXWATERMARKS__RX8DATAWATERMARK 24 870 #define W_RXWATERMARKS__RX8DATAWATERMARK 7 871 #define O_RXWATERMARKS__RX9DATAWATERMARK 16 872 #define W_RXWATERMARKS__RX9DATAWATERMARK 7 873 #define O_RXWATERMARKS__RX10DATAWATERMARK 8 874 #define W_RXWATERMARKS__RX10DATAWATERMARK 7 875 #define O_RXWATERMARKS__RX11DATAWATERMARK 0 876 #define W_RXWATERMARKS__RX11DATAWATERMARK 7 877 #define R_RXWATERMARKS4 0x248 878 #define O_RXWATERMARKS__RX12DATAWATERMARK 24 879 #define W_RXWATERMARKS__RX12DATAWATERMARK 7 880 #define O_RXWATERMARKS__RX13DATAWATERMARK 16 881 #define W_RXWATERMARKS__RX13DATAWATERMARK 7 882 #define O_RXWATERMARKS__RX14DATAWATERMARK 8 883 #define W_RXWATERMARKS__RX14DATAWATERMARK 7 884 #define O_RXWATERMARKS__RX15DATAWATERMARK 0 885 #define W_RXWATERMARKS__RX15DATAWATERMARK 7 886 #define R_FREEWATERMARKS 0x249 887 #define O_FREEWATERMARKS__FREEOUTWATERMARK 16 888 #define W_FREEWATERMARKS__FREEOUTWATERMARK 16 889 #define O_FREEWATERMARKS__JUMFRWATERMARK 8 890 #define W_FREEWATERMARKS__JUMFRWATERMARK 7 891 #define O_FREEWATERMARKS__REGFRWATERMARK 0 892 #define W_FREEWATERMARKS__REGFRWATERMARK 7 893 #define R_EGRESSFIFOCARVINGSLOTS 0x24a 894 895 #define CTRL_RES0 0 896 #define CTRL_RES1 1 897 #define CTRL_REG_FREE 2 898 #define CTRL_JUMBO_FREE 3 899 #define CTRL_CONT 4 900 #define CTRL_EOP 5 901 #define CTRL_START 6 902 #define CTRL_SNGL 7 903 904 #define CTRL_B0_NOT_EOP 0 905 #define CTRL_B0_EOP 1 906 907 #define R_ROUND_ROBIN_TABLE 0 908 #define R_PDE_CLASS_0 0x300 909 #define R_PDE_CLASS_1 0x302 910 #define R_PDE_CLASS_2 0x304 911 #define R_PDE_CLASS_3 0x306 912 913 #define R_MSG_TX_THRESHOLD 0x308 914 915 #define R_GMAC_JFR0_BUCKET_SIZE 0x320 916 #define R_GMAC_RFR0_BUCKET_SIZE 0x321 917 #define R_GMAC_TX0_BUCKET_SIZE 0x322 918 #define R_GMAC_TX1_BUCKET_SIZE 0x323 919 #define R_GMAC_TX2_BUCKET_SIZE 0x324 920 #define R_GMAC_TX3_BUCKET_SIZE 0x325 921 #define R_GMAC_JFR1_BUCKET_SIZE 0x326 922 #define R_GMAC_RFR1_BUCKET_SIZE 0x327 923 924 #define R_XGS_TX0_BUCKET_SIZE 0x320 925 #define R_XGS_TX1_BUCKET_SIZE 0x321 926 #define R_XGS_TX2_BUCKET_SIZE 0x322 927 #define R_XGS_TX3_BUCKET_SIZE 0x323 928 #define R_XGS_TX4_BUCKET_SIZE 0x324 929 #define R_XGS_TX5_BUCKET_SIZE 0x325 930 #define R_XGS_TX6_BUCKET_SIZE 0x326 931 #define R_XGS_TX7_BUCKET_SIZE 0x327 932 #define R_XGS_TX8_BUCKET_SIZE 0x328 933 #define R_XGS_TX9_BUCKET_SIZE 0x329 934 #define R_XGS_TX10_BUCKET_SIZE 0x32A 935 #define R_XGS_TX11_BUCKET_SIZE 0x32B 936 #define R_XGS_TX12_BUCKET_SIZE 0x32C 937 #define R_XGS_TX13_BUCKET_SIZE 0x32D 938 #define R_XGS_TX14_BUCKET_SIZE 0x32E 939 #define R_XGS_TX15_BUCKET_SIZE 0x32F 940 #define R_XGS_JFR_BUCKET_SIZE 0x330 941 #define R_XGS_RFR_BUCKET_SIZE 0x331 942 943 #define R_CC_CPU0_0 0x380 944 #define R_CC_CPU1_0 0x388 945 #define R_CC_CPU2_0 0x390 946 #define R_CC_CPU3_0 0x398 947 #define R_CC_CPU4_0 0x3a0 948 #define R_CC_CPU5_0 0x3a8 949 #define R_CC_CPU6_0 0x3b0 950 #define R_CC_CPU7_0 0x3b8 951 952 #define XLR_GMAC_BLK_SZ (XLR_IO_GMAC_1_OFFSET - \ 953 XLR_IO_GMAC_0_OFFSET) 954 955 /* Constants used for configuring the devices */ 956 957 #define XLR_FB_STN 6 /* Bucket used for Tx freeback */ 958 959 #define MAC_B2B_IPG 88 960 961 #define XLR_NET_PREPAD_LEN 32 962 963 /* frame sizes need to be cacheline aligned */ 964 #define MAX_FRAME_SIZE (1536 + XLR_NET_PREPAD_LEN) 965 #define MAX_FRAME_SIZE_JUMBO 9216 966 967 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES 968 #define MAC_PREPAD 0 969 #define BYTE_OFFSET 2 970 #define XLR_RX_BUF_SIZE (MAX_FRAME_SIZE + BYTE_OFFSET + \ 971 MAC_PREPAD + MAC_SKB_BACK_PTR_SIZE + SMP_CACHE_BYTES) 972 #define MAC_CRC_LEN 4 973 #define MAX_NUM_MSGRNG_STN_CC 128 974 #define MAX_MSG_SND_ATTEMPTS 100 /* 13 stns x 4 entry msg/stn + 975 * headroom 976 */ 977 978 #define MAC_FRIN_TO_BE_SENT_THRESHOLD 16 979 980 #define MAX_NUM_DESC_SPILL 1024 981 #define MAX_FRIN_SPILL (MAX_NUM_DESC_SPILL << 2) 982 #define MAX_FROUT_SPILL (MAX_NUM_DESC_SPILL << 2) 983 #define MAX_CLASS_0_SPILL (MAX_NUM_DESC_SPILL << 2) 984 #define MAX_CLASS_1_SPILL (MAX_NUM_DESC_SPILL << 2) 985 #define MAX_CLASS_2_SPILL (MAX_NUM_DESC_SPILL << 2) 986 #define MAX_CLASS_3_SPILL (MAX_NUM_DESC_SPILL << 2) 987 988 enum { 989 SGMII_SPEED_10 = 0x00000000, 990 SGMII_SPEED_100 = 0x02000000, 991 SGMII_SPEED_1000 = 0x04000000, 992 }; 993 994 enum tsv_rsv_reg { 995 TX_RX_64_BYTE_FRAME = 0x20, 996 TX_RX_64_127_BYTE_FRAME, 997 TX_RX_128_255_BYTE_FRAME, 998 TX_RX_256_511_BYTE_FRAME, 999 TX_RX_512_1023_BYTE_FRAME, 1000 TX_RX_1024_1518_BYTE_FRAME, 1001 TX_RX_1519_1522_VLAN_BYTE_FRAME, 1002 1003 RX_BYTE_COUNTER = 0x27, 1004 RX_PACKET_COUNTER, 1005 RX_FCS_ERROR_COUNTER, 1006 RX_MULTICAST_PACKET_COUNTER, 1007 RX_BROADCAST_PACKET_COUNTER, 1008 RX_CONTROL_FRAME_PACKET_COUNTER, 1009 RX_PAUSE_FRAME_PACKET_COUNTER, 1010 RX_UNKNOWN_OP_CODE_COUNTER, 1011 RX_ALIGNMENT_ERROR_COUNTER, 1012 RX_FRAME_LENGTH_ERROR_COUNTER, 1013 RX_CODE_ERROR_COUNTER, 1014 RX_CARRIER_SENSE_ERROR_COUNTER, 1015 RX_UNDERSIZE_PACKET_COUNTER, 1016 RX_OVERSIZE_PACKET_COUNTER, 1017 RX_FRAGMENTS_COUNTER, 1018 RX_JABBER_COUNTER, 1019 RX_DROP_PACKET_COUNTER, 1020 1021 TX_BYTE_COUNTER = 0x38, 1022 TX_PACKET_COUNTER, 1023 TX_MULTICAST_PACKET_COUNTER, 1024 TX_BROADCAST_PACKET_COUNTER, 1025 TX_PAUSE_CONTROL_FRAME_COUNTER, 1026 TX_DEFERRAL_PACKET_COUNTER, 1027 TX_EXCESSIVE_DEFERRAL_PACKET_COUNTER, 1028 TX_SINGLE_COLLISION_PACKET_COUNTER, 1029 TX_MULTI_COLLISION_PACKET_COUNTER, 1030 TX_LATE_COLLISION_PACKET_COUNTER, 1031 TX_EXCESSIVE_COLLISION_PACKET_COUNTER, 1032 TX_TOTAL_COLLISION_COUNTER, 1033 TX_PAUSE_FRAME_HONERED_COUNTER, 1034 TX_DROP_FRAME_COUNTER, 1035 TX_JABBER_FRAME_COUNTER, 1036 TX_FCS_ERROR_COUNTER, 1037 TX_CONTROL_FRAME_COUNTER, 1038 TX_OVERSIZE_FRAME_COUNTER, 1039 TX_UNDERSIZE_FRAME_COUNTER, 1040 TX_FRAGMENT_FRAME_COUNTER, 1041 1042 CARRY_REG_1 = 0x4c, 1043 CARRY_REG_2 = 0x4d, 1044 }; 1045 1046 struct xlr_adapter { 1047 struct net_device *netdev[4]; 1048 }; 1049 1050 struct xlr_net_priv { 1051 u32 __iomem *base_addr; 1052 struct net_device *ndev; 1053 struct xlr_adapter *adapter; 1054 struct mii_bus *mii_bus; 1055 int num_rx_desc; 1056 int phy_addr; /* PHY addr on MDIO bus */ 1057 int pcs_id; /* PCS id on MDIO bus */ 1058 int port_id; /* Port(gmac/xgmac) number, i.e 0-7 */ 1059 int tx_stnid; 1060 u32 __iomem *mii_addr; 1061 u32 __iomem *serdes_addr; 1062 u32 __iomem *pcs_addr; 1063 u32 __iomem *gpio_addr; 1064 int phy_speed; 1065 int port_type; 1066 struct timer_list queue_timer; 1067 int wakeup_q; 1068 struct platform_device *pdev; 1069 struct xlr_net_data *nd; 1070 1071 u64 *frin_spill; 1072 u64 *frout_spill; 1073 u64 *class_0_spill; 1074 u64 *class_1_spill; 1075 u64 *class_2_spill; 1076 u64 *class_3_spill; 1077 }; 1078 1079 void xlr_set_gmac_speed(struct xlr_net_priv *priv); 1080