1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * linux/drivers/net/ethernet/amd/am79c961a.h 4 */ 5 6 #ifndef _LINUX_am79c961a_H 7 #define _LINUX_am79c961a_H 8 9 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */ 10 #define DEBUG_TX 2 11 #define DEBUG_RX 4 12 #define DEBUG_INT 8 13 #define DEBUG_IC 16 14 #ifndef NET_DEBUG 15 #define NET_DEBUG 0 16 #endif 17 18 #define NET_UID 0 19 #define NET_RDP 0x10 20 #define NET_RAP 0x12 21 #define NET_RESET 0x14 22 #define NET_IDP 0x16 23 24 /* 25 * RAP registers 26 */ 27 #define CSR0 0 28 #define CSR0_INIT 0x0001 29 #define CSR0_STRT 0x0002 30 #define CSR0_STOP 0x0004 31 #define CSR0_TDMD 0x0008 32 #define CSR0_TXON 0x0010 33 #define CSR0_RXON 0x0020 34 #define CSR0_IENA 0x0040 35 #define CSR0_INTR 0x0080 36 #define CSR0_IDON 0x0100 37 #define CSR0_TINT 0x0200 38 #define CSR0_RINT 0x0400 39 #define CSR0_MERR 0x0800 40 #define CSR0_MISS 0x1000 41 #define CSR0_CERR 0x2000 42 #define CSR0_BABL 0x4000 43 #define CSR0_ERR 0x8000 44 45 #define CSR3 3 46 #define CSR3_EMBA 0x0008 47 #define CSR3_DXMT2PD 0x0010 48 #define CSR3_LAPPEN 0x0020 49 #define CSR3_DXSUFLO 0x0040 50 #define CSR3_IDONM 0x0100 51 #define CSR3_TINTM 0x0200 52 #define CSR3_RINTM 0x0400 53 #define CSR3_MERRM 0x0800 54 #define CSR3_MISSM 0x1000 55 #define CSR3_BABLM 0x4000 56 #define CSR3_MASKALL 0x5F00 57 58 #define CSR4 4 59 #define CSR4_JABM 0x0001 60 #define CSR4_JAB 0x0002 61 #define CSR4_TXSTRTM 0x0004 62 #define CSR4_TXSTRT 0x0008 63 #define CSR4_RCVCCOM 0x0010 64 #define CSR4_RCVCCO 0x0020 65 #define CSR4_MFCOM 0x0100 66 #define CSR4_MFCO 0x0200 67 #define CSR4_ASTRP_RCV 0x0400 68 #define CSR4_APAD_XMIT 0x0800 69 70 #define CTRL1 5 71 #define CTRL1_SPND 0x0001 72 73 #define LADRL 8 74 #define LADRM1 9 75 #define LADRM2 10 76 #define LADRH 11 77 #define PADRL 12 78 #define PADRM 13 79 #define PADRH 14 80 81 #define MODE 15 82 #define MODE_DISRX 0x0001 83 #define MODE_DISTX 0x0002 84 #define MODE_LOOP 0x0004 85 #define MODE_DTCRC 0x0008 86 #define MODE_COLL 0x0010 87 #define MODE_DRETRY 0x0020 88 #define MODE_INTLOOP 0x0040 89 #define MODE_PORT_AUI 0x0000 90 #define MODE_PORT_10BT 0x0080 91 #define MODE_DRXPA 0x2000 92 #define MODE_DRXBA 0x4000 93 #define MODE_PROMISC 0x8000 94 95 #define BASERXL 24 96 #define BASERXH 25 97 #define BASETXL 30 98 #define BASETXH 31 99 100 #define POLLINT 47 101 102 #define SIZERXR 76 103 #define SIZETXR 78 104 105 #define CSR_MFC 112 106 107 #define RMD_ENP 0x0100 108 #define RMD_STP 0x0200 109 #define RMD_CRC 0x0800 110 #define RMD_FRAM 0x2000 111 #define RMD_ERR 0x4000 112 #define RMD_OWN 0x8000 113 114 #define TMD_ENP 0x0100 115 #define TMD_STP 0x0200 116 #define TMD_MORE 0x1000 117 #define TMD_ERR 0x4000 118 #define TMD_OWN 0x8000 119 120 #define TST_RTRY 0x0400 121 #define TST_LCAR 0x0800 122 #define TST_LCOL 0x1000 123 #define TST_UFLO 0x4000 124 #define TST_BUFF 0x8000 125 126 #define ISALED0 0x0004 127 #define ISALED0_LNKST 0x8000 128 129 struct dev_priv { 130 unsigned long rxbuffer[RX_BUFFERS]; 131 unsigned long txbuffer[TX_BUFFERS]; 132 unsigned char txhead; 133 unsigned char txtail; 134 unsigned char rxhead; 135 unsigned char rxtail; 136 unsigned long rxhdr; 137 unsigned long txhdr; 138 spinlock_t chip_lock; 139 struct timer_list timer; 140 struct net_device *dev; 141 }; 142 143 #endif 144