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Searched refs:PCIO (Results 1 – 9 of 9) sorted by relevance

/drivers/video/fbdev/nvidia/
Dnv_setup.c62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVWriteCrtc()
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value); in NVWriteCrtc()
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVReadCrtc()
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); in NVReadCrtc()
94 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); in NVWriteAttr()
99 VGA_WR08(par->PCIO, VGA_ATT_IW, index); in NVWriteAttr()
100 VGA_WR08(par->PCIO, VGA_ATT_W, value); in NVWriteAttr()
106 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a); in NVReadAttr()
111 VGA_WR08(par->PCIO, VGA_ATT_IW, index); in NVReadAttr()
112 return (VGA_RD08(par->PCIO, VGA_ATT_R)); in NVReadAttr()
[all …]
Dnv_hw.c61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); in NVLockUnlock()
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); in NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); in NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); in NVLockUnlock()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); in NVShowHideCursor()
80 VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1); in NVShowHideCursor()
1544 VGA_WR08(par->PCIO, 0x03D4, 0x53); in NVLoadStateExt()
1545 VGA_WR08(par->PCIO, 0x03D5, state->timingH); in NVLoadStateExt()
1546 VGA_WR08(par->PCIO, 0x03D4, 0x54); in NVLoadStateExt()
[all …]
Dnvidia.c435 VGA_WR08(par->PCIO, 0x03D4, 0x1C); in nvidia_calc_regs()
436 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); in nvidia_calc_regs()
635 VGA_WR08(par->PCIO, 0x03D4, 0x44); in nvidiafb_set_par()
636 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); in nvidiafb_set_par()
650 VGA_WR08(par->PCIO, 0x3d4, 0x46); in nvidiafb_set_par()
651 tmp = VGA_RD08(par->PCIO, 0x3d5); in nvidiafb_set_par()
653 VGA_WR08(par->PCIO, 0x3d5, tmp); in nvidiafb_set_par()
Dnv_type.h169 volatile u8 __iomem *PCIO; member
/drivers/video/fbdev/riva/
Drivafb-i2c.c33 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setscl()
34 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; in riva_gpio_setscl()
41 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setscl()
42 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); in riva_gpio_setscl()
51 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setsda()
52 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; in riva_gpio_setsda()
59 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setsda()
60 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); in riva_gpio_setsda()
69 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); in riva_gpio_getscl()
70 if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04) in riva_gpio_getscl()
[all …]
Driva_hw.c92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); in vgaLockUnlock()
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); in vgaLockUnlock()
96 VGA_WR08(chip->PCIO, 0x3D5, cr11); in vgaLockUnlock()
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F); in nv4LockUnlock()
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in nv4LockUnlock()
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31); in ShowHideCursor()
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); in ShowHideCursor()
1489 VGA_WR08(chip->PCIO, 0x03D4, 0x44); in LoadStateExt()
1490 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); in LoadStateExt()
1654 VGA_WR08(chip->PCIO, 0x03D4, 0x53); in LoadStateExt()
[all …]
Dnv_driver.c404 par->riva.PCIO = par->riva.PCIO0 + 0x2000; in riva_common_setup()
409 par->riva.PCIO = par->riva.PCIO0; in riva_common_setup()
Dfbdev.c387 VGA_WR08(par->riva.PCIO, 0x3d4, index); in CRTCout()
388 VGA_WR08(par->riva.PCIO, 0x3d5, val); in CRTCout()
394 VGA_WR08(par->riva.PCIO, 0x3d4, index); in CRTCin()
395 return (VGA_RD08(par->riva.PCIO, 0x3d5)); in CRTCin()
429 VGA_WR08(par->riva.PCIO, 0x3c0, index); in ATTRout()
430 VGA_WR08(par->riva.PCIO, 0x3c0, val); in ATTRout()
436 VGA_WR08(par->riva.PCIO, 0x3c0, index); in ATTRin()
437 return (VGA_RD08(par->riva.PCIO, 0x3c1)); in ATTRin()
Driva_hw.h457 volatile U008 __iomem *PCIO; member