Searched refs:PEXTDEV (Results 1 – 7 of 7) sorted by relevance
/drivers/video/fbdev/riva/ |
D | nvreg.h | 98 #define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value) 99 #define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg) 100 #define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg) 101 #define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value) 102 #define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value) 103 #define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask)
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D | riva_hw.c | 628 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv3UpdateArbitrationSettings() 820 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv4UpdateArbitrationSettings() 1085 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv10UpdateArbitrationSettings() 2013 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv3GetConfig() 2070 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv4GetConfig() 2154 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? in nv10GetConfig() 2168 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) in nv10GetConfig()
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D | nv_driver.c | 326 par->riva.PEXTDEV = in riva_common_setup()
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D | riva_hw.h | 450 volatile U032 __iomem *PEXTDEV; member
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/drivers/video/fbdev/nvidia/ |
D | nv_setup.c | 223 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ? in nv4GetConfig() 261 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ? in nv10GetConfig() 265 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22)) in nv10GetConfig() 304 par->PEXTDEV = par->REGS + (0x00101000 / 4); in NVCommonSetup()
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D | nv_type.h | 162 volatile u32 __iomem *PEXTDEV; member
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D | nv_hw.c | 395 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? in nv4UpdateArbitrationSettings() 635 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? in nv10UpdateArbitrationSettings()
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