Searched refs:PHASE (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.h | 60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
83 SRII(PHASE, DP_DTO, 2),\
84 SRII(PHASE, DP_DTO, 3),\
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| D | dce_clock_source.c | 931 REG_WRITE(PHASE[inst], clock_100hz); in dce112_program_pix_clk()
1010 clock_hz = REG_READ(PHASE[inst]); in get_pixel_clk_frequency_100hz()
1108 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); in dcn3_program_pix_clk()
1112 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); in dcn3_program_pix_clk()
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| /drivers/gpu/drm/nouveau/dispnv50/ |
| D | head917d.c | 44 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head917d_dither()
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| D | headc37d.c | 100 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in headc37d_dither()
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| D | head507d.c | 62 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head507d_dither()
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| D | head907d.c | 91 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head907d_dither()
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| /drivers/scsi/ |
| D | FlashPoint.c | 527 #define PHASE BIT(13) macro
1838 && !((RDW_HARPOON((ioport + hp_intstat)) & PHASE) in FlashPoint_HandleInterrupt()
1865 (PROG_HLT | RSEL | PHASE | BUS_FREE)); in FlashPoint_HandleInterrupt()
1901 (PHASE | IUNKWN | PROG_HLT)); in FlashPoint_HandleInterrupt()
2089 (PROG_HLT | TIMEOUT | SEL | BUS_FREE | PHASE | in FPT_SccbMgr_bad_isr()
2677 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2682 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2755 (PHASE | RESET)) in FPT_sres()
2837 while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) && in FPT_sres()
2847 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_SendMsg()
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