Searched refs:PLL_RESET_N (Results 1 – 3 of 3) sorted by relevance
| /drivers/clk/qcom/ |
| D | clk-pll.c | 22 #define PLL_RESET_N BIT(2) macro
30 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
53 PLL_RESET_N); in clk_pll_enable()
75 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_disable()
147 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_set_rate()
286 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_sr2_enable()
287 PLL_RESET_N); in clk_pll_sr2_enable()
307 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_sr2_set_rate()
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| D | clk-hfpll.c | 17 #define PLL_RESET_N BIT(2) macro
72 regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); in __clk_hfpll_enable()
98 if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) in clk_hfpll_enable()
115 PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); in __clk_hfpll_disable()
207 if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { in clk_hfpll_init()
234 return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); in hfpll_is_enabled()
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| D | clk-alpha-pll.c | 18 # define PLL_RESET_N BIT(2) macro
335 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_alpha_pll_enable()
365 PLL_RESET_N, PLL_RESET_N); in clk_alpha_pll_enable()
404 mask = PLL_RESET_N | PLL_BYPASSNL; in clk_alpha_pll_disable()
848 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_disable()
1045 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_fabia_pll_configure()
1084 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, in alpha_pll_fabia_enable()
1085 PLL_RESET_N); in alpha_pll_fabia_enable()
1191 if (val & PLL_RESET_N) in alpha_pll_fabia_prepare()
1445 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); in clk_trion_pll_configure()
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