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Searched refs:REGS (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/msm/adreno/
Da6xx_gpu_state.h279 #define REGS(_array, _sel_reg, _sel_val) \ macro
284 REGS(a6xx_registers, 0, 0),
285 REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
286 REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
315 REGS(a6xx_ahb_registers, 0, 0),
319 REGS(a6xx_vbif_registers, 0, 0);
322 REGS(a6xx_gbif_registers, 0, 0);
364 REGS(a6xx_gmu_cx_registers, 0, 0),
365 REGS(a6xx_gmu_cx_rscc_registers, 0, 0),
366 REGS(a6xx_gmu_gx_registers, 0, 0),
/drivers/video/fbdev/nvidia/
Dnv_setup.c298 par->PRAMIN = par->REGS + (0x00710000 / 4); in NVCommonSetup()
299 par->PCRTC0 = par->REGS + (0x00600000 / 4); in NVCommonSetup()
300 par->PRAMDAC0 = par->REGS + (0x00680000 / 4); in NVCommonSetup()
301 par->PFB = par->REGS + (0x00100000 / 4); in NVCommonSetup()
302 par->PFIFO = par->REGS + (0x00002000 / 4); in NVCommonSetup()
303 par->PGRAPH = par->REGS + (0x00400000 / 4); in NVCommonSetup()
304 par->PEXTDEV = par->REGS + (0x00101000 / 4); in NVCommonSetup()
305 par->PTIMER = par->REGS + (0x00009000 / 4); in NVCommonSetup()
306 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
307 par->FIFO = par->REGS + (0x00800000 / 4); in NVCommonSetup()
[all …]
Dnv_type.h155 volatile u32 __iomem *REGS; member
Dnvidia.c1211 id = NV_RD32(par->REGS, 0x1800); in nvidia_get_chipset()
1327 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); in nvidiafb_probe()
1329 if (!par->REGS) { in nvidiafb_probe()
1416 iounmap(par->REGS); in nvidiafb_probe()
1441 iounmap(par->REGS); in nvidiafb_remove()
Dnv_hw.c1225 j = NV_RD32(par->REGS, 0x1540) & 0xff; in NVLoadStateExt()
/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_reg.h43 #define REG(reg) (REGS)->offset.reg
45 #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field
Ddmub_dcn21.c36 #define REGS dmub->regs macro
Ddmub_dcn30.c36 #define REGS dmub->regs macro
Ddmub_dcn20.c37 #define REGS dmub->regs macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c605 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v4_2_set_dcm()
Duvd_v3_1.c207 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v3_1_set_dcm()
/drivers/memory/tegra/
Dtegra210-emc-cc-r21021.c33 #define REGS (1 << 30) macro