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Searched refs:REG_DSI_7nm_PHY_PLL_CMODE_1 (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_7nm.c330 pll_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */ in dsi_pll_commit()
/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h2303 #define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250 macro