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Searched refs:REG_GET (Results 1 – 25 of 78) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubp.c696 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); in hubp2_dmdata_status_done()
882 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); in hubp2_enable_triplebuffer()
896 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); in hubp2_is_triplebuffer_enabled()
917 REG_GET(DCSURF_FLIP_CONTROL, in hubp2_is_flip_pending()
920 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, in hubp2_is_flip_pending()
923 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, in hubp2_is_flip_pending()
1079 REG_GET(HUBPRET_CONTROL, in hubp2_read_state_common()
1092 REG_GET(BLANK_OFFSET_1, in hubp2_read_state_common()
1095 REG_GET(DST_DIMENSIONS, in hubp2_read_state_common()
1115 REG_GET(REF_FREQ_TO_PIX_FREQ, in hubp2_read_state_common()
[all …]
Ddcn20_stream_encoder.c350 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc2_read_state()
352 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc2_read_state()
353 REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num); in enc2_read_state()
355 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc2_read_state()
356 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc2_read_state()
358 REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable); in enc2_read_state()
359 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc2_read_state()
430 REG_GET(DP_SEC_METADATA_TRANSMISSION, in enc2_stream_encoder_update_dp_info_packets()
Ddcn20_link_encoder.c194 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active); in enc2_fec_is_active()
206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); in link_enc2_read_state()
207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); in link_enc2_read_state()
208 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); in link_enc2_read_state()
209 REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); in link_enc2_read_state()
279 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); in dcn20_link_encoder_get_max_link_cap()
294 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); in dcn20_link_encoder_is_in_alt_mode()
Ddcn20_dsc.c157 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); in dsc2_read_state()
158 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); in dsc2_read_state()
159 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); in dsc2_read_state()
160 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); in dsc2_read_state()
161 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); in dsc2_read_state()
162 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); in dsc2_read_state()
163 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); in dsc2_read_state()
164 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); in dsc2_read_state()
238 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_enable()
263 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); in dsc2_disable()
Ddcn20_dwb.c177 REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked); in dwb2_update()
204 REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled); in dwb2_is_enabled()
205 REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en); in dwb2_is_enabled()
Ddcn20_dpp.c56 REG_GET(DPP_CONTROL, in dpp20_read_state()
58 REG_GET(CM_DGAM_CONTROL, in dpp20_read_state()
63 REG_GET(CM_GAMUT_REMAP_CONTROL, in dpp20_read_state()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubp.c88 REG_GET(VBLANK_PARAMETERS_5, in apply_DEDCN21_142_wa_for_hostvm_deadline()
96 REG_GET(VBLANK_PARAMETERS_6, in apply_DEDCN21_142_wa_for_hostvm_deadline()
104 REG_GET(FLIP_PARAMETERS_3, in apply_DEDCN21_142_wa_for_hostvm_deadline()
112 REG_GET(FLIP_PARAMETERS_4, in apply_DEDCN21_142_wa_for_hostvm_deadline()
265 REG_GET(HUBPRET_CONTROL, in hubp21_validate_dml_output()
358 REG_GET(BLANK_OFFSET_1, in hubp21_validate_dml_output()
360 REG_GET(DST_DIMENSIONS, in hubp21_validate_dml_output()
365 REG_GET(REF_FREQ_TO_PIX_FREQ, in hubp21_validate_dml_output()
391 REG_GET(VBLANK_PARAMETERS_1, in hubp21_validate_dml_output()
394 REG_GET(NOM_PARAMETERS_0, in hubp21_validate_dml_output()
[all …]
Ddcn21_hubbub.c78 REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active); in dcn21_dchvm_init()
626 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, in hubbub21_wm_read_state()
629 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, in hubbub21_wm_read_state()
632 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, in hubbub21_wm_read_state()
635 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, in hubbub21_wm_read_state()
640 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, in hubbub21_wm_read_state()
643 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, in hubbub21_wm_read_state()
646 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, in hubbub21_wm_read_state()
649 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, in hubbub21_wm_read_state()
654 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, in hubbub21_wm_read_state()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubp.c95 REG_GET(DCHUBP_CNTL, in hubp1_get_underflow_status()
740 REG_GET(DCSURF_FLIP_CONTROL, in hubp1_is_flip_pending()
743 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, in hubp1_is_flip_pending()
746 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, in hubp1_is_flip_pending()
876 REG_GET(HUBPRET_CONTROL, in hubp1_read_state_common()
889 REG_GET(BLANK_OFFSET_1, in hubp1_read_state_common()
892 REG_GET(DST_DIMENSIONS, in hubp1_read_state_common()
912 REG_GET(REF_FREQ_TO_PIX_FREQ, in hubp1_read_state_common()
916 REG_GET(VBLANK_PARAMETERS_1, in hubp1_read_state_common()
919 REG_GET(VBLANK_PARAMETERS_3, in hubp1_read_state_common()
[all …]
Ddcn10_mpc.c146 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_is_mpcc_idle()
147 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
148 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); in mpc1_is_mpcc_idle()
160 REG_GET(MPCC_TOP_SEL[mpcc_id], in mpc1_assert_mpcc_idle_before_connect()
392 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_mpc_init_single_inst()
419 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); in mpc1_init_mpcc_list_from_hw()
423 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
424 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_init_mpcc_list_from_hw()
425 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); in mpc1_init_mpcc_list_from_hw()
439 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
[all …]
Ddcn10_optc.c628 REG_GET(OTG_STATUS_FRAME_COUNT, in optc1_get_vblank_counter()
676 REG_GET(OTG_NOM_VERT_POSITION, in optc1_get_position()
700 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, in optc1_did_triggered_reset_occur()
703 REG_GET(OTG_VERT_SYNC_CONTROL, in optc1_did_triggered_reset_occur()
727 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_enable_reset_trigger()
1277 REG_GET(OTG_STEREO_STATUS, in optc1_is_stereo_left_eye()
1314 REG_GET(OTG_CONTROL, in optc1_read_otg_state()
1321 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_read_otg_state()
1324 REG_GET(OTG_V_TOTAL, in optc1_read_otg_state()
1327 REG_GET(OTG_V_TOTAL_MAX, in optc1_read_otg_state()
[all …]
Ddcn10_dpp.c99 REG_GET(DPP_CONTROL, in dpp_read_state()
101 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
103 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
105 REG_GET(CM_DGAM_CONTROL, in dpp_read_state()
107 REG_GET(CM_RGAM_CONTROL, in dpp_read_state()
109 REG_GET(CM_GAMUT_REMAP_CONTROL, in dpp_read_state()
Ddcn10_link_encoder.c457 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); in dcn10_get_dig_frontend()
541 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); in dcn10_is_dig_enabled()
1314 REG_GET(DP_MSE_SAT_UPDATE, in dcn10_link_encoder_update_mst_stream_allocation_table()
1317 REG_GET(DP_MSE_SAT_UPDATE, in dcn10_link_encoder_update_mst_stream_allocation_table()
1337 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); in dcn10_link_encoder_connect_dig_be_to_fe()
1418 REG_GET(DIG_BE_CNTL, DIG_MODE, &value); in dcn10_get_dig_mode()
Ddcn10_dpp_cm.c204 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_cm_program_color_matrix()
461 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_program_input_csc()
644 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_degamma_ram_inuse()
736 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_ingamma_ram_inuse()
806 REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num); in dpp1_program_input_lut()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_panel_cntl.c59 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dce_get_16_bit_backlight_from_pwm()
60 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dce_get_16_bit_backlight_from_pwm()
63 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in dce_get_16_bit_backlight_from_pwm()
64 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dce_get_16_bit_backlight_from_pwm()
109 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_panel_cntl_hw_init()
137 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_panel_cntl_hw_init()
165 REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state); in dce_is_panel_backlight_on()
178 REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dce_is_panel_powered_on()
196 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_store_backlight_level()
Ddce_i2c_hw.c77 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in get_channel_status()
124 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); in process_channel_reply()
136 REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status); in is_engine_available()
140 REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate); in is_engine_available()
151 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in is_hw_busy()
273 REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div); in set_speed()
349 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in release_engine()
/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
46 REG_GET(A_reg, A, &gpio->store.a); in store_registers()
47 REG_GET(EN_reg, EN, &gpio->store.en); in store_registers()
86 REG_GET(Y_reg, Y, value); in dal_hw_gpio_get_value()
/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_dcn20.c69 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn20_get_fb_base_offset()
72 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn20_get_fb_base_offset()
90 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn20_reset()
280 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); in dmub_dcn20_is_hw_init()
289 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn20_is_supported()
Ddmub_dcn30.c68 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn30_get_fb_base_offset()
71 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn30_get_fb_base_offset()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_stream_encoder.c407 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc3_read_state()
409 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc3_read_state()
410 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); in enc3_read_state()
412 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc3_read_state()
413 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc3_read_state()
415 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); in enc3_read_state()
416 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc3_read_state()
470 REG_GET(DP_SEC_METADATA_TRANSMISSION, in enc3_stream_encoder_update_dp_info_packets()
Ddcn30_dwb.c144 REG_GET(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, &pre_locked); in dwb3_update()
177 REG_GET(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, &dwb_enabled); in dwb3_is_enabled()
178 REG_GET(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, &fc_frame_capture_en); in dwb3_is_enabled()
Ddcn30_mpc.c54 REG_GET(DWB_MUX[dwb_id], MPC_DWB0_MUX_STATUS, &status); in mpc3_is_dwb_idle()
429 REG_GET(SHAPER_CONTROL[rmu_idx], in mpc3_get_shaper_current()
809 REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, &power_status_shaper); in mpc3_power_on_shaper_3dlut()
810 REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, &power_status_3dlut); in mpc3_power_on_shaper_3dlut()
814 REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, &power_status_shaper); in mpc3_power_on_shaper_3dlut()
815 REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, &power_status_3dlut); in mpc3_power_on_shaper_3dlut()
896 REG_GET(RMU_3DLUT_MODE[rmu_idx], in get3dlut_config()
899 REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[rmu_idx], in get3dlut_config()
921 REG_GET(RMU_3DLUT_MODE[rmu_idx], MPC_RMU_3DLUT_SIZE, &lut_size); in get3dlut_config()
1107 REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], MPCC_GAMUT_REMAP_MODE_CURRENT, &gamut_mode); in mpc3_set_gamut_remap()
[all …]
Ddcn30_dpp_cm.c64 REG_GET(CM_GAMCOR_CONTROL, in dpp30_get_gamcor_current()
71 REG_GET(CM_GAMCOR_CONTROL, in dpp30_get_gamcor_current()
143 REG_GET(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, &power_status); in dpp3_power_on_gamcor_lut()
398 REG_GET(CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, &gamut_mode); in dpp3_cm_set_gamut_remap()
/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_core.c43 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi4_core_ddc_init()
110 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi4_core_ddc_read()
115 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi4_core_ddc_read()
124 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi4_core_ddc_read()
131 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi4_core_ddc_read()
139 buf[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi4_core_ddc_read()
/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi4_core.c44 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
116 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
121 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
130 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
137 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
145 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()

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