| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v2_0.c | 61 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_0_get_invalidate_req()
63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in gfxhub_v2_0_get_invalidate_req()
64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gfxhub_v2_0_get_invalidate_req()
65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gfxhub_v2_0_get_invalidate_req()
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gfxhub_v2_0_get_invalidate_req()
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gfxhub_v2_0_get_invalidate_req()
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gfxhub_v2_0_get_invalidate_req()
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_0_get_invalidate_req()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_0_init_tlb_regs()
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| D | gfxhub_v1_0.c | 126 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
128 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
130 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in gfxhub_v1_0_init_tlb_regs()
133 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
135 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
146 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_0_init_cache_regs()
149 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in gfxhub_v1_0_init_cache_regs()
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| D | gfxhub_v2_1.c | 61 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_1_get_invalidate_req()
63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in gfxhub_v2_1_get_invalidate_req()
64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gfxhub_v2_1_get_invalidate_req()
65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gfxhub_v2_1_get_invalidate_req()
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gfxhub_v2_1_get_invalidate_req()
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gfxhub_v2_1_get_invalidate_req()
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gfxhub_v2_1_get_invalidate_req()
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_1_get_invalidate_req()
192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_1_init_tlb_regs()
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| D | mmhub_v2_0.c | 102 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_0_get_invalidate_req()
104 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in mmhub_v2_0_get_invalidate_req()
105 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in mmhub_v2_0_get_invalidate_req()
106 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in mmhub_v2_0_get_invalidate_req()
107 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in mmhub_v2_0_get_invalidate_req()
108 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in mmhub_v2_0_get_invalidate_req()
109 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in mmhub_v2_0_get_invalidate_req()
110 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_0_get_invalidate_req()
226 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_0_init_system_aperture_regs()
238 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
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| D | mmhub_v1_0.c | 131 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs()
143 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
147 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
149 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); in mmhub_v1_0_init_tlb_regs()
150 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
152 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in mmhub_v1_0_init_tlb_regs()
166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
167 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_0_init_cache_regs()
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| D | gmc_v7_0.c | 101 blackout = REG_SET_FIELD(blackout, in gmc_v7_0_mc_stop()
115 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v7_0_mc_resume()
118 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v7_0_mc_resume()
119 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v7_0_mc_resume()
281 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v7_0_mc_program()
286 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v7_0_mc_program()
306 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); in gmc_v7_0_mc_program()
525 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
527 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
529 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v7_0_set_fault_enable_default()
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| D | dce_v10_0.c | 244 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, in dce_v10_0_page_flip()
315 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); in dce_v10_0_hpd_set_polarity()
317 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); in dce_v10_0_hpd_set_polarity()
351 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); in dce_v10_0_hpd_init()
357 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); in dce_v10_0_hpd_init()
361 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v10_0_hpd_init()
364 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v10_0_hpd_init()
399 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); in dce_v10_0_hpd_fini()
451 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); in dce_v10_0_set_vga_render_state()
453 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in dce_v10_0_set_vga_render_state()
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| D | navi10_ih.c | 69 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
71 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
73 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in force_update_wptr_for_self_int()
78 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, in force_update_wptr_for_self_int()
95 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in navi10_ih_enable_interrupts()
96 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in navi10_ih_enable_interrupts()
110 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in navi10_ih_enable_interrupts()
126 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, in navi10_ih_enable_interrupts()
152 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in navi10_ih_disable_interrupts()
153 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in navi10_ih_disable_interrupts()
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| D | gmc_v8_0.c | 189 blackout = REG_SET_FIELD(blackout, in gmc_v8_0_mc_stop()
203 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v8_0_mc_resume()
206 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v8_0_mc_resume()
207 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v8_0_mc_resume()
472 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v8_0_mc_program()
477 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v8_0_mc_program()
508 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); in gmc_v8_0_mc_program()
756 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
758 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
760 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
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| D | vega10_ih.c | 51 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in vega10_ih_enable_interrupts()
52 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in vega10_ih_enable_interrupts()
65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in vega10_ih_enable_interrupts()
81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, in vega10_ih_enable_interrupts()
107 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in vega10_ih_disable_interrupts()
108 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in vega10_ih_disable_interrupts()
126 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in vega10_ih_disable_interrupts()
146 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, in vega10_ih_disable_interrupts()
170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
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| D | dce_v11_0.c | 262 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, in dce_v11_0_page_flip()
333 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); in dce_v11_0_hpd_set_polarity()
335 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); in dce_v11_0_hpd_set_polarity()
369 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); in dce_v11_0_hpd_init()
375 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); in dce_v11_0_hpd_init()
379 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v11_0_hpd_init()
382 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v11_0_hpd_init()
416 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); in dce_v11_0_hpd_fini()
467 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); in dce_v11_0_set_vga_render_state()
469 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in dce_v11_0_set_vga_render_state()
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| D | nbio_v2_3.c | 98 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v2_3_sdma_doorbell_range()
101 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v2_3_sdma_doorbell_range()
105 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v2_3_sdma_doorbell_range()
121 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v2_3_vcn_doorbell_range()
124 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v2_3_vcn_doorbell_range()
127 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v2_3_vcn_doorbell_range()
146 tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, in nbio_v2_3_enable_doorbell_selfring_aperture()
148 REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, in nbio_v2_3_enable_doorbell_selfring_aperture()
150 REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, in nbio_v2_3_enable_doorbell_selfring_aperture()
170 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, in nbio_v2_3_ih_doorbell_range()
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| D | nbio_v6_1.c | 79 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v6_1_sdma_doorbell_range()
80 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); in nbio_v6_1_sdma_doorbell_range()
82 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); in nbio_v6_1_sdma_doorbell_range()
100 …tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN… in nbio_v6_1_enable_doorbell_selfring_aperture()
101 …REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1)… in nbio_v6_1_enable_doorbell_selfring_aperture()
102 …REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); in nbio_v6_1_enable_doorbell_selfring_aperture()
120 …ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index… in nbio_v6_1_ih_doorbell_range()
121 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, in nbio_v6_1_ih_doorbell_range()
124 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); in nbio_v6_1_ih_doorbell_range()
139 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in nbio_v6_1_ih_control()
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| D | tonga_ih.c | 64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in tonga_ih_enable_interrupts()
65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts()
81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in tonga_ih_disable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts()
117 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in tonga_ih_irq_init()
119 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); in tonga_ih_irq_init()
126 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in tonga_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); in tonga_ih_irq_init()
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| D | nbio_v7_4.c | 122 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v7_4_sdma_doorbell_range()
123 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); in nbio_v7_4_sdma_doorbell_range()
125 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); in nbio_v7_4_sdma_doorbell_range()
144 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v7_4_vcn_doorbell_range()
147 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v7_4_vcn_doorbell_range()
150 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v7_4_vcn_doorbell_range()
168 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | in nbio_v7_4_enable_doorbell_selfring_aperture()
169 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | in nbio_v7_4_enable_doorbell_selfring_aperture()
170 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); in nbio_v7_4_enable_doorbell_selfring_aperture()
187 …ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index… in nbio_v7_4_ih_doorbell_range()
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| D | iceland_ih.c | 65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in iceland_ih_enable_interrupts()
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in iceland_ih_enable_interrupts()
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in iceland_ih_disable_interrupts()
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in iceland_ih_disable_interrupts()
121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in iceland_ih_irq_init()
123 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); in iceland_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in iceland_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in iceland_ih_irq_init()
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| D | cz_ih.c | 65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in cz_ih_enable_interrupts()
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in cz_ih_enable_interrupts()
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in cz_ih_disable_interrupts()
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in cz_ih_disable_interrupts()
121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in cz_ih_irq_init()
123 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); in cz_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in cz_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in cz_ih_irq_init()
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| D | mes_v10_1.c | 421 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); in mes_v10_1_enable()
430 data = REG_SET_FIELD(data, CP_MES_DC_OP_CNTL, in mes_v10_1_enable()
435 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); in mes_v10_1_enable()
439 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); in mes_v10_1_enable()
440 data = REG_SET_FIELD(data, CP_MES_CNTL, in mes_v10_1_enable()
442 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); in mes_v10_1_enable()
443 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); in mes_v10_1_enable()
506 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); in mes_v10_1_load_microcode()
507 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); in mes_v10_1_load_microcode()
526 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); in mes_v10_1_load_microcode()
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| D | mmhub_v9_4.c | 167 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v9_4_init_system_aperture_regs()
185 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, in mmhub_v9_4_init_tlb_regs()
187 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, in mmhub_v9_4_init_tlb_regs()
189 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, in mmhub_v9_4_init_tlb_regs()
191 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, in mmhub_v9_4_init_tlb_regs()
193 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, in mmhub_v9_4_init_tlb_regs()
195 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, in mmhub_v9_4_init_tlb_regs()
197 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, in mmhub_v9_4_init_tlb_regs()
211 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, in mmhub_v9_4_init_cache_regs()
213 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, in mmhub_v9_4_init_cache_regs()
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| D | smu_v11_0_i2c.c | 55 reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0); in smu_v11_0_i2c_set_clock_gating()
82 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1); in smu_v11_0_i2c_configure()
83 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1); in smu_v11_0_i2c_configure()
84 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0); in smu_v11_0_i2c_configure()
85 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0); in smu_v11_0_i2c_configure()
87 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2); in smu_v11_0_i2c_configure()
88 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1); in smu_v11_0_i2c_configure()
261 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART, in smu_v11_0_i2c_transmit()
263 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]); in smu_v11_0_i2c_transmit()
268 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP, in smu_v11_0_i2c_transmit()
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| D | nbio_v7_0.c | 86 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); in nbio_v7_0_sdma_doorbell_range()
87 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); in nbio_v7_0_sdma_doorbell_range()
89 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); in nbio_v7_0_sdma_doorbell_range()
102 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v7_0_vcn_doorbell_range()
105 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v7_0_vcn_doorbell_range()
108 doorbell_range = REG_SET_FIELD(doorbell_range, in nbio_v7_0_vcn_doorbell_range()
132 …ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index… in nbio_v7_0_ih_doorbell_range()
133 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); in nbio_v7_0_ih_doorbell_range()
135 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); in nbio_v7_0_ih_doorbell_range()
242 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in nbio_v7_0_ih_control()
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| D | nv.c | 151 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); in nv_grbm_select()
152 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); in nv_grbm_select()
153 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); in nv_grbm_select()
154 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); in nv_grbm_select()
953 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in nv_update_hdp_mem_power_gating()
955 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in nv_update_hdp_mem_power_gating()
961 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in nv_update_hdp_mem_power_gating()
963 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in nv_update_hdp_mem_power_gating()
965 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in nv_update_hdp_mem_power_gating()
967 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in nv_update_hdp_mem_power_gating()
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| D | amdgpu_amdkfd_gfx_v10_3.c | 217 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, in hqd_load_v10_3()
232 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, in hqd_load_v10_3()
279 REG_SET_FIELD(m->cp_hqd_eop_rptr, in hqd_load_v10_3()
282 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); in hqd_load_v10_3()
408 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, in hqd_sdma_load_v10_3()
438 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, in hqd_sdma_load_v10_3()
633 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
635 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
637 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
681 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
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| D | dce_v6_0.c | 1125 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, in dce_v6_0_audio_select_pin()
1160 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v6_0_audio_write_latency_fields()
1162 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v6_0_audio_write_latency_fields()
1165 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v6_0_audio_write_latency_fields()
1167 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v6_0_audio_write_latency_fields()
1210 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v6_0_audio_write_speaker_allocation()
1212 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v6_0_audio_write_speaker_allocation()
1216 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v6_0_audio_write_speaker_allocation()
1219 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v6_0_audio_write_speaker_allocation()
1223 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v6_0_audio_write_speaker_allocation()
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega10_thermal.c | 142 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
145 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
162 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
166 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
278 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega10_fan_ctrl_set_fan_speed_percent()
326 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), in vega10_fan_ctrl_set_fan_speed_rpm()
395 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); in vega10_thermal_set_temperature_range()
396 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); in vega10_thermal_set_temperature_range()
397 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high); in vega10_thermal_set_temperature_range()
398 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low); in vega10_thermal_set_temperature_range()
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