1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
6 *
7 */
8 #include <linux/clk.h>
9 #include <linux/iopoll.h>
10 #include <linux/of.h>
11 #include <linux/module.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/property.h>
14 #include <linux/regmap.h>
15 #include <linux/sys_soc.h>
16
17 #include "cqhci.h"
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
20
21 /* CTL_CFG Registers */
22 #define CTL_CFG_2 0x14
23 #define CTL_CFG_3 0x18
24
25 #define SLOTTYPE_MASK GENMASK(31, 30)
26 #define SLOTTYPE_EMBEDDED BIT(30)
27 #define TUNINGFORSDR50_MASK BIT(13)
28
29 /* PHY Registers */
30 #define PHY_CTRL1 0x100
31 #define PHY_CTRL2 0x104
32 #define PHY_CTRL3 0x108
33 #define PHY_CTRL4 0x10C
34 #define PHY_CTRL5 0x110
35 #define PHY_CTRL6 0x114
36 #define PHY_STAT1 0x130
37 #define PHY_STAT2 0x134
38
39 #define IOMUX_ENABLE_SHIFT 31
40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
41 #define OTAPDLYENA_SHIFT 20
42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
43 #define OTAPDLYSEL_SHIFT 12
44 #define OTAPDLYSEL_MASK GENMASK(15, 12)
45 #define STRBSEL_SHIFT 24
46 #define STRBSEL_4BIT_MASK GENMASK(27, 24)
47 #define STRBSEL_8BIT_MASK GENMASK(31, 24)
48 #define SEL50_SHIFT 8
49 #define SEL50_MASK BIT(SEL50_SHIFT)
50 #define SEL100_SHIFT 9
51 #define SEL100_MASK BIT(SEL100_SHIFT)
52 #define FREQSEL_SHIFT 8
53 #define FREQSEL_MASK GENMASK(10, 8)
54 #define CLKBUFSEL_SHIFT 0
55 #define CLKBUFSEL_MASK GENMASK(2, 0)
56 #define DLL_TRIM_ICP_SHIFT 4
57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
58 #define DR_TY_SHIFT 20
59 #define DR_TY_MASK GENMASK(22, 20)
60 #define ENDLL_SHIFT 1
61 #define ENDLL_MASK BIT(ENDLL_SHIFT)
62 #define DLLRDY_SHIFT 0
63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
64 #define PDB_SHIFT 0
65 #define PDB_MASK BIT(PDB_SHIFT)
66 #define CALDONE_SHIFT 1
67 #define CALDONE_MASK BIT(CALDONE_SHIFT)
68 #define RETRIM_SHIFT 17
69 #define RETRIM_MASK BIT(RETRIM_SHIFT)
70 #define SELDLYTXCLK_SHIFT 17
71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
72 #define SELDLYRXCLK_SHIFT 16
73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
74 #define ITAPDLYSEL_SHIFT 0
75 #define ITAPDLYSEL_MASK GENMASK(4, 0)
76 #define ITAPDLYENA_SHIFT 8
77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
78 #define ITAPCHGWIN_SHIFT 9
79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
80
81 #define DRIVER_STRENGTH_50_OHM 0x0
82 #define DRIVER_STRENGTH_33_OHM 0x1
83 #define DRIVER_STRENGTH_66_OHM 0x2
84 #define DRIVER_STRENGTH_100_OHM 0x3
85 #define DRIVER_STRENGTH_40_OHM 0x4
86
87 #define CLOCK_TOO_SLOW_HZ 50000000
88
89 /* Command Queue Host Controller Interface Base address */
90 #define SDHCI_AM654_CQE_BASE_ADDR 0x200
91
92 static struct regmap_config sdhci_am654_regmap_config = {
93 .reg_bits = 32,
94 .val_bits = 32,
95 .reg_stride = 4,
96 .fast_io = true,
97 };
98
99 struct timing_data {
100 const char *otap_binding;
101 const char *itap_binding;
102 u32 capability;
103 };
104
105 static const struct timing_data td[] = {
106 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
107 "ti,itap-del-sel-legacy",
108 0},
109 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
110 "ti,itap-del-sel-mmc-hs",
111 MMC_CAP_MMC_HIGHSPEED},
112 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
113 "ti,itap-del-sel-sd-hs",
114 MMC_CAP_SD_HIGHSPEED},
115 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
116 "ti,itap-del-sel-sdr12",
117 MMC_CAP_UHS_SDR12},
118 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
119 "ti,itap-del-sel-sdr25",
120 MMC_CAP_UHS_SDR25},
121 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
122 NULL,
123 MMC_CAP_UHS_SDR50},
124 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
125 NULL,
126 MMC_CAP_UHS_SDR104},
127 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
128 NULL,
129 MMC_CAP_UHS_DDR50},
130 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
131 "ti,itap-del-sel-ddr52",
132 MMC_CAP_DDR},
133 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
134 NULL,
135 MMC_CAP2_HS200},
136 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
137 NULL,
138 MMC_CAP2_HS400},
139 };
140
141 struct sdhci_am654_data {
142 struct regmap *base;
143 bool legacy_otapdly;
144 int otap_del_sel[ARRAY_SIZE(td)];
145 int itap_del_sel[ARRAY_SIZE(td)];
146 int clkbuf_sel;
147 int trm_icp;
148 int drv_strength;
149 int strb_sel;
150 u32 flags;
151 u32 quirks;
152
153 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
154 };
155
156 struct sdhci_am654_driver_data {
157 const struct sdhci_pltfm_data *pdata;
158 u32 flags;
159 #define IOMUX_PRESENT (1 << 0)
160 #define FREQSEL_2_BIT (1 << 1)
161 #define STRBSEL_4_BIT (1 << 2)
162 #define DLL_PRESENT (1 << 3)
163 #define DLL_CALIB (1 << 4)
164 };
165
sdhci_am654_setup_dll(struct sdhci_host * host,unsigned int clock)166 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
167 {
168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
169 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
170 int sel50, sel100, freqsel;
171 u32 mask, val;
172 int ret;
173
174 /* Disable delay chain mode */
175 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
176 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
177
178 if (sdhci_am654->flags & FREQSEL_2_BIT) {
179 switch (clock) {
180 case 200000000:
181 sel50 = 0;
182 sel100 = 0;
183 break;
184 case 100000000:
185 sel50 = 0;
186 sel100 = 1;
187 break;
188 default:
189 sel50 = 1;
190 sel100 = 0;
191 }
192
193 /* Configure PHY DLL frequency */
194 mask = SEL50_MASK | SEL100_MASK;
195 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
196 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
197
198 } else {
199 switch (clock) {
200 case 200000000:
201 freqsel = 0x0;
202 break;
203 default:
204 freqsel = 0x4;
205 }
206
207 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
208 freqsel << FREQSEL_SHIFT);
209 }
210 /* Configure DLL TRIM */
211 mask = DLL_TRIM_ICP_MASK;
212 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
213
214 /* Configure DLL driver strength */
215 mask |= DR_TY_MASK;
216 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
217 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
218
219 /* Enable DLL */
220 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
221 0x1 << ENDLL_SHIFT);
222 /*
223 * Poll for DLL ready. Use a one second timeout.
224 * Works in all experiments done so far
225 */
226 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
227 val & DLLRDY_MASK, 1000, 1000000);
228 if (ret) {
229 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
230 return;
231 }
232 }
233
sdhci_am654_write_itapdly(struct sdhci_am654_data * sdhci_am654,u32 itapdly)234 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
235 u32 itapdly)
236 {
237 /* Set ITAPCHGWIN before writing to ITAPDLY */
238 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
239 1 << ITAPCHGWIN_SHIFT);
240 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
241 itapdly << ITAPDLYSEL_SHIFT);
242 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
243 }
244
sdhci_am654_setup_delay_chain(struct sdhci_am654_data * sdhci_am654,unsigned char timing)245 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
246 unsigned char timing)
247 {
248 u32 mask, val;
249
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
251
252 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
253 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
254 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
255
256 sdhci_am654_write_itapdly(sdhci_am654,
257 sdhci_am654->itap_del_sel[timing]);
258 }
259
sdhci_am654_set_clock(struct sdhci_host * host,unsigned int clock)260 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
261 {
262 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
263 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
264 unsigned char timing = host->mmc->ios.timing;
265 u32 otap_del_sel;
266 u32 otap_del_ena;
267 u32 mask, val;
268
269 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
270
271 sdhci_set_clock(host, clock);
272
273 /* Setup DLL Output TAP delay */
274 if (sdhci_am654->legacy_otapdly)
275 otap_del_sel = sdhci_am654->otap_del_sel[0];
276 else
277 otap_del_sel = sdhci_am654->otap_del_sel[timing];
278
279 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
280
281 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
282 val = (otap_del_ena << OTAPDLYENA_SHIFT) |
283 (otap_del_sel << OTAPDLYSEL_SHIFT);
284
285 /* Write to STRBSEL for HS400 speed mode */
286 if (timing == MMC_TIMING_MMC_HS400) {
287 if (sdhci_am654->flags & STRBSEL_4_BIT)
288 mask |= STRBSEL_4BIT_MASK;
289 else
290 mask |= STRBSEL_8BIT_MASK;
291
292 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
293 }
294
295 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
296
297 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ)
298 sdhci_am654_setup_dll(host, clock);
299 else
300 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
301
302 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
303 sdhci_am654->clkbuf_sel);
304 }
305
sdhci_j721e_4bit_set_clock(struct sdhci_host * host,unsigned int clock)306 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
307 unsigned int clock)
308 {
309 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
310 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
311 unsigned char timing = host->mmc->ios.timing;
312 u32 otap_del_sel;
313 u32 mask, val;
314
315 /* Setup DLL Output TAP delay */
316 if (sdhci_am654->legacy_otapdly)
317 otap_del_sel = sdhci_am654->otap_del_sel[0];
318 else
319 otap_del_sel = sdhci_am654->otap_del_sel[timing];
320
321 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
322 val = (0x1 << OTAPDLYENA_SHIFT) |
323 (otap_del_sel << OTAPDLYSEL_SHIFT);
324 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
325
326 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
327 sdhci_am654->clkbuf_sel);
328
329 sdhci_set_clock(host, clock);
330 }
331
sdhci_am654_write_power_on(struct sdhci_host * host,u8 val,int reg)332 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
333 {
334 writeb(val, host->ioaddr + reg);
335 usleep_range(1000, 10000);
336 return readb(host->ioaddr + reg);
337 }
338
339 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */
sdhci_am654_write_b(struct sdhci_host * host,u8 val,int reg)340 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
341 {
342 unsigned char timing = host->mmc->ios.timing;
343 u8 pwr;
344 int ret;
345
346 if (reg == SDHCI_HOST_CONTROL) {
347 switch (timing) {
348 /*
349 * According to the data manual, HISPD bit
350 * should not be set in these speed modes.
351 */
352 case MMC_TIMING_SD_HS:
353 case MMC_TIMING_MMC_HS:
354 val &= ~SDHCI_CTRL_HISPD;
355 }
356 }
357
358 writeb(val, host->ioaddr + reg);
359 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
360 /*
361 * Power on will not happen until the card detect debounce
362 * timer expires. Wait at least 1.5 seconds for the power on
363 * bit to be set
364 */
365 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
366 pwr & SDHCI_POWER_ON, 0,
367 MAX_POWER_ON_TIMEOUT, false, host, val,
368 reg);
369 if (ret)
370 dev_info(mmc_dev(host->mmc), "Power on failed\n");
371 }
372 }
373
sdhci_am654_reset(struct sdhci_host * host,u8 mask)374 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
375 {
376 u8 ctrl;
377 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
378 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
379
380 sdhci_and_cqhci_reset(host, mask);
381
382 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
383 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
384 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
385 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
386 }
387 }
388
sdhci_am654_execute_tuning(struct mmc_host * mmc,u32 opcode)389 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
390 {
391 struct sdhci_host *host = mmc_priv(mmc);
392 int err = sdhci_execute_tuning(mmc, opcode);
393
394 if (err)
395 return err;
396 /*
397 * Tuning data remains in the buffer after tuning.
398 * Do a command and data reset to get rid of it
399 */
400 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
401
402 return 0;
403 }
404
sdhci_am654_cqhci_irq(struct sdhci_host * host,u32 intmask)405 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
406 {
407 int cmd_error = 0;
408 int data_error = 0;
409
410 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
411 return intmask;
412
413 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
414
415 return 0;
416 }
417
418 #define ITAP_MAX 32
sdhci_am654_platform_execute_tuning(struct sdhci_host * host,u32 opcode)419 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
420 u32 opcode)
421 {
422 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
423 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
424 int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
425 u32 itap;
426
427 /* Enable ITAPDLY */
428 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
429 1 << ITAPDLYENA_SHIFT);
430
431 for (itap = 0; itap < ITAP_MAX; itap++) {
432 sdhci_am654_write_itapdly(sdhci_am654, itap);
433
434 cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
435 if (cur_val && !prev_val)
436 pass_window = itap;
437
438 if (!cur_val)
439 fail_len++;
440
441 prev_val = cur_val;
442 }
443 /*
444 * Having determined the length of the failing window and start of
445 * the passing window calculate the length of the passing window and
446 * set the final value halfway through it considering the range as a
447 * circular buffer
448 */
449 pass_len = ITAP_MAX - fail_len;
450 itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
451 sdhci_am654_write_itapdly(sdhci_am654, itap);
452
453 return 0;
454 }
455
456 static struct sdhci_ops sdhci_am654_ops = {
457 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
458 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
459 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
460 .set_uhs_signaling = sdhci_set_uhs_signaling,
461 .set_bus_width = sdhci_set_bus_width,
462 .set_power = sdhci_set_power_and_bus_voltage,
463 .set_clock = sdhci_am654_set_clock,
464 .write_b = sdhci_am654_write_b,
465 .irq = sdhci_am654_cqhci_irq,
466 .reset = sdhci_and_cqhci_reset,
467 };
468
469 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
470 .ops = &sdhci_am654_ops,
471 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
472 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
473 };
474
475 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
476 .pdata = &sdhci_am654_pdata,
477 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
478 DLL_CALIB,
479 };
480
481 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
482 .pdata = &sdhci_am654_pdata,
483 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
484 };
485
486 static struct sdhci_ops sdhci_j721e_8bit_ops = {
487 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
488 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
489 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
490 .set_uhs_signaling = sdhci_set_uhs_signaling,
491 .set_bus_width = sdhci_set_bus_width,
492 .set_power = sdhci_set_power_and_bus_voltage,
493 .set_clock = sdhci_am654_set_clock,
494 .write_b = sdhci_am654_write_b,
495 .irq = sdhci_am654_cqhci_irq,
496 .reset = sdhci_and_cqhci_reset,
497 };
498
499 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
500 .ops = &sdhci_j721e_8bit_ops,
501 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
502 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
503 };
504
505 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
506 .pdata = &sdhci_j721e_8bit_pdata,
507 .flags = DLL_PRESENT | DLL_CALIB,
508 };
509
510 static struct sdhci_ops sdhci_j721e_4bit_ops = {
511 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
512 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
513 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
514 .set_uhs_signaling = sdhci_set_uhs_signaling,
515 .set_bus_width = sdhci_set_bus_width,
516 .set_power = sdhci_set_power_and_bus_voltage,
517 .set_clock = sdhci_j721e_4bit_set_clock,
518 .write_b = sdhci_am654_write_b,
519 .irq = sdhci_am654_cqhci_irq,
520 .reset = sdhci_am654_reset,
521 };
522
523 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
524 .ops = &sdhci_j721e_4bit_ops,
525 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
526 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
527 };
528
529 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
530 .pdata = &sdhci_j721e_4bit_pdata,
531 .flags = IOMUX_PRESENT,
532 };
533
534 static const struct soc_device_attribute sdhci_am654_devices[] = {
535 { .family = "AM65X",
536 .revision = "SR1.0",
537 .data = &sdhci_am654_sr1_drvdata
538 },
539 {/* sentinel */}
540 };
541
sdhci_am654_dumpregs(struct mmc_host * mmc)542 static void sdhci_am654_dumpregs(struct mmc_host *mmc)
543 {
544 sdhci_dumpregs(mmc_priv(mmc));
545 }
546
547 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
548 .enable = sdhci_cqe_enable,
549 .disable = sdhci_cqe_disable,
550 .dumpregs = sdhci_am654_dumpregs,
551 };
552
sdhci_am654_cqe_add_host(struct sdhci_host * host)553 static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
554 {
555 struct cqhci_host *cq_host;
556 int ret;
557
558 cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host),
559 GFP_KERNEL);
560 if (!cq_host)
561 return -ENOMEM;
562
563 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
564 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
565 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
566 cq_host->ops = &sdhci_am654_cqhci_ops;
567
568 host->mmc->caps2 |= MMC_CAP2_CQE;
569
570 ret = cqhci_init(cq_host, host->mmc, 1);
571
572 return ret;
573 }
574
sdhci_am654_get_otap_delay(struct sdhci_host * host,struct sdhci_am654_data * sdhci_am654)575 static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
576 struct sdhci_am654_data *sdhci_am654)
577 {
578 struct device *dev = mmc_dev(host->mmc);
579 int i;
580 int ret;
581
582 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding,
583 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
584 if (ret) {
585 /*
586 * ti,otap-del-sel-legacy is mandatory, look for old binding
587 * if not found.
588 */
589 ret = device_property_read_u32(dev, "ti,otap-del-sel",
590 &sdhci_am654->otap_del_sel[0]);
591 if (ret) {
592 dev_err(dev, "Couldn't find otap-del-sel\n");
593
594 return ret;
595 }
596
597 dev_info(dev, "Using legacy binding ti,otap-del-sel\n");
598 sdhci_am654->legacy_otapdly = true;
599
600 return 0;
601 }
602
603 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) {
604
605 ret = device_property_read_u32(dev, td[i].otap_binding,
606 &sdhci_am654->otap_del_sel[i]);
607 if (ret) {
608 dev_dbg(dev, "Couldn't find %s\n",
609 td[i].otap_binding);
610 /*
611 * Remove the corresponding capability
612 * if an otap-del-sel value is not found
613 */
614 if (i <= MMC_TIMING_MMC_DDR52)
615 host->mmc->caps &= ~td[i].capability;
616 else
617 host->mmc->caps2 &= ~td[i].capability;
618 }
619
620 if (td[i].itap_binding)
621 device_property_read_u32(dev, td[i].itap_binding,
622 &sdhci_am654->itap_del_sel[i]);
623 }
624
625 return 0;
626 }
627
sdhci_am654_init(struct sdhci_host * host)628 static int sdhci_am654_init(struct sdhci_host *host)
629 {
630 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
631 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
632 u32 ctl_cfg_2 = 0;
633 u32 mask;
634 u32 val;
635 int ret;
636
637 /* Reset OTAP to default value */
638 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
639 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
640
641 if (sdhci_am654->flags & DLL_CALIB) {
642 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
643 if (~val & CALDONE_MASK) {
644 /* Calibrate IO lines */
645 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
646 PDB_MASK, PDB_MASK);
647 ret = regmap_read_poll_timeout(sdhci_am654->base,
648 PHY_STAT1, val,
649 val & CALDONE_MASK,
650 1, 20);
651 if (ret)
652 return ret;
653 }
654 }
655
656 /* Enable pins by setting IO mux to 0 */
657 if (sdhci_am654->flags & IOMUX_PRESENT)
658 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
659 IOMUX_ENABLE_MASK, 0);
660
661 /* Set slot type based on SD or eMMC */
662 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
663 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
664
665 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
666 ctl_cfg_2);
667
668 /* Enable tuning for SDR50 */
669 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
670 TUNINGFORSDR50_MASK);
671
672 ret = sdhci_setup_host(host);
673 if (ret)
674 return ret;
675
676 ret = sdhci_am654_cqe_add_host(host);
677 if (ret)
678 goto err_cleanup_host;
679
680 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
681 if (ret)
682 goto err_cleanup_host;
683
684 ret = __sdhci_add_host(host);
685 if (ret)
686 goto err_cleanup_host;
687
688 return 0;
689
690 err_cleanup_host:
691 sdhci_cleanup_host(host);
692 return ret;
693 }
694
sdhci_am654_get_of_property(struct platform_device * pdev,struct sdhci_am654_data * sdhci_am654)695 static int sdhci_am654_get_of_property(struct platform_device *pdev,
696 struct sdhci_am654_data *sdhci_am654)
697 {
698 struct device *dev = &pdev->dev;
699 int drv_strength;
700 int ret;
701
702 if (sdhci_am654->flags & DLL_PRESENT) {
703 ret = device_property_read_u32(dev, "ti,trm-icp",
704 &sdhci_am654->trm_icp);
705 if (ret)
706 return ret;
707
708 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
709 &drv_strength);
710 if (ret)
711 return ret;
712
713 switch (drv_strength) {
714 case 50:
715 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
716 break;
717 case 33:
718 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
719 break;
720 case 66:
721 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
722 break;
723 case 100:
724 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
725 break;
726 case 40:
727 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
728 break;
729 default:
730 dev_err(dev, "Invalid driver strength\n");
731 return -EINVAL;
732 }
733 }
734
735 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
736 device_property_read_u32(dev, "ti,clkbuf-sel",
737 &sdhci_am654->clkbuf_sel);
738
739 if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
740 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
741
742 sdhci_get_of_property(pdev);
743
744 return 0;
745 }
746
747 static const struct of_device_id sdhci_am654_of_match[] = {
748 {
749 .compatible = "ti,am654-sdhci-5.1",
750 .data = &sdhci_am654_drvdata,
751 },
752 {
753 .compatible = "ti,j721e-sdhci-8bit",
754 .data = &sdhci_j721e_8bit_drvdata,
755 },
756 {
757 .compatible = "ti,j721e-sdhci-4bit",
758 .data = &sdhci_j721e_4bit_drvdata,
759 },
760 { /* sentinel */ }
761 };
762 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
763
sdhci_am654_probe(struct platform_device * pdev)764 static int sdhci_am654_probe(struct platform_device *pdev)
765 {
766 const struct sdhci_am654_driver_data *drvdata;
767 const struct soc_device_attribute *soc;
768 struct sdhci_pltfm_host *pltfm_host;
769 struct sdhci_am654_data *sdhci_am654;
770 const struct of_device_id *match;
771 struct sdhci_host *host;
772 struct clk *clk_xin;
773 struct device *dev = &pdev->dev;
774 void __iomem *base;
775 int ret;
776
777 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
778 drvdata = match->data;
779
780 /* Update drvdata based on SoC revision */
781 soc = soc_device_match(sdhci_am654_devices);
782 if (soc && soc->data)
783 drvdata = soc->data;
784
785 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
786 if (IS_ERR(host))
787 return PTR_ERR(host);
788
789 pltfm_host = sdhci_priv(host);
790 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
791 sdhci_am654->flags = drvdata->flags;
792
793 clk_xin = devm_clk_get(dev, "clk_xin");
794 if (IS_ERR(clk_xin)) {
795 dev_err(dev, "clk_xin clock not found.\n");
796 ret = PTR_ERR(clk_xin);
797 goto err_pltfm_free;
798 }
799
800 pltfm_host->clk = clk_xin;
801
802 /* Clocks are enabled using pm_runtime */
803 pm_runtime_enable(dev);
804 ret = pm_runtime_get_sync(dev);
805 if (ret < 0) {
806 pm_runtime_put_noidle(dev);
807 goto pm_runtime_disable;
808 }
809
810 base = devm_platform_ioremap_resource(pdev, 1);
811 if (IS_ERR(base)) {
812 ret = PTR_ERR(base);
813 goto pm_runtime_put;
814 }
815
816 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
817 &sdhci_am654_regmap_config);
818 if (IS_ERR(sdhci_am654->base)) {
819 dev_err(dev, "Failed to initialize regmap\n");
820 ret = PTR_ERR(sdhci_am654->base);
821 goto pm_runtime_put;
822 }
823
824 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
825 if (ret)
826 goto pm_runtime_put;
827
828 ret = mmc_of_parse(host->mmc);
829 if (ret) {
830 dev_err(dev, "parsing dt failed (%d)\n", ret);
831 goto pm_runtime_put;
832 }
833
834 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
835
836 ret = sdhci_am654_init(host);
837 if (ret)
838 goto pm_runtime_put;
839
840 return 0;
841
842 pm_runtime_put:
843 pm_runtime_put_sync(dev);
844 pm_runtime_disable:
845 pm_runtime_disable(dev);
846 err_pltfm_free:
847 sdhci_pltfm_free(pdev);
848 return ret;
849 }
850
sdhci_am654_remove(struct platform_device * pdev)851 static int sdhci_am654_remove(struct platform_device *pdev)
852 {
853 struct sdhci_host *host = platform_get_drvdata(pdev);
854 int ret;
855
856 sdhci_remove_host(host, true);
857 ret = pm_runtime_put_sync(&pdev->dev);
858 if (ret < 0)
859 return ret;
860
861 pm_runtime_disable(&pdev->dev);
862 sdhci_pltfm_free(pdev);
863
864 return 0;
865 }
866
867 static struct platform_driver sdhci_am654_driver = {
868 .driver = {
869 .name = "sdhci-am654",
870 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
871 .of_match_table = sdhci_am654_of_match,
872 },
873 .probe = sdhci_am654_probe,
874 .remove = sdhci_am654_remove,
875 };
876
877 module_platform_driver(sdhci_am654_driver);
878
879 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
880 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
881 MODULE_LICENSE("GPL");
882