Searched refs:RING_MI_MODE (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/i915/gt/ |
| D | intel_ring_submission.c | 138 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); in flush_cs_tlb()
166 RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING)); in stop_ring()
168 RING_MI_MODE(engine->mmio_base), in stop_ring()
309 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in xcs_resume()
1028 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); in ring_release()
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| D | intel_engine_cs.c | 1013 const i915_reg_t mode = RING_MI_MODE(base); in intel_engine_stop_cs()
1042 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in intel_engine_cancel_stop_cs()
1188 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) in ring_is_idle()
1448 ENGINE_READ(engine, RING_MI_MODE), in intel_engine_print_registers()
1449 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); in intel_engine_print_registers()
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| D | intel_lrc.c | 2701 ENGINE_READ(engine, RING_MI_MODE)); in process_csb()
4141 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in enable_execlists()
4157 if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) { in unexpected_starting_state()
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| D | selftest_lrc.c | 4921 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
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| /drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.c | 70 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
122 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
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| D | handlers.c | 1987 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, in init_generic_mmio_info()
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| /drivers/gpu/drm/i915/ |
| D | i915_pmu.c | 312 val = ENGINE_READ_FW(engine, RING_MI_MODE); in engine_sample()
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| D | i915_gpu_error.c | 1165 ee->mode = ENGINE_READ(engine, RING_MI_MODE); in engine_record_registers()
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| D | i915_reg.h | 2689 #define RING_MI_MODE(base) _MMIO((base) + 0x9c) macro
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