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Searched refs:SCF_COEF_MEM_CTRL (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/hisilicon/kirin/
Dkirin_drm_dpe.c315 writel(0x00000088, base + DPE_RCH_VG0_SCL_OFFSET + SCF_COEF_MEM_CTRL); in dpe_clk_enable()
321 writel(0x00000088, base + DPE_RCH_VG1_SCL_OFFSET + SCF_COEF_MEM_CTRL); in dpe_clk_enable()
325 writel(0x00000088, base + DPE_RCH_VG2_SCL_OFFSET + SCF_COEF_MEM_CTRL); in dpe_clk_enable()
328 writel(0x00000088, base + DPE_RCH_G0_SCL_OFFSET + SCF_COEF_MEM_CTRL); in dpe_clk_enable()
332 writel(0x00000088, base + DPE_RCH_G1_SCL_OFFSET + SCF_COEF_MEM_CTRL); in dpe_clk_enable()
Dkirin_dpe_reg.h203 #define SCF_COEF_MEM_CTRL (0x0018) macro