1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Secure Digital Host Controller
4 //
5 // Copyright (C) 2018 Spreadtrum, Inc.
6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
7
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/highmem.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_gpio.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/slab.h>
20
21 #include "sdhci-pltfm.h"
22 #include "mmc_hsq.h"
23
24 /* SDHCI_ARGUMENT2 register high 16bit */
25 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
26
27 #define SDHCI_SPRD_REG_32_DLL_CFG 0x200
28 #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
29 #define SDHCI_SPRD_DLL_EN BIT(21)
30 #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16)
31 #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00
32 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3
33
34 #define SDHCI_SPRD_REG_32_DLL_DLY 0x204
35
36 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
37 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
38 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
39 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
40 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
41
42 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
43 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
44 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
45
46 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C
47 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
48 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
49
50 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
51
52 /* SDHCI_HOST_CONTROL2 */
53 #define SDHCI_SPRD_CTRL_HS200 0x0005
54 #define SDHCI_SPRD_CTRL_HS400 0x0006
55 #define SDHCI_SPRD_CTRL_HS400ES 0x0007
56
57 /*
58 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
59 * reserved, and only used on Spreadtrum's design, the hardware cannot work
60 * if this bit is cleared.
61 * 1 : normal work
62 * 0 : hardware reset
63 */
64 #define SDHCI_HW_RESET_CARD BIT(3)
65
66 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF
67 #define SDHCI_SPRD_CLK_MAX_DIV 1023
68
69 #define SDHCI_SPRD_CLK_DEF_RATE 26000000
70 #define SDHCI_SPRD_PHY_DLL_CLK 52000000
71
72 struct sdhci_sprd_host {
73 u32 version;
74 struct clk *clk_sdio;
75 struct clk *clk_enable;
76 struct clk *clk_2x_enable;
77 struct pinctrl *pinctrl;
78 struct pinctrl_state *pins_uhs;
79 struct pinctrl_state *pins_default;
80 u32 base_rate;
81 int flags; /* backup of host attribute */
82 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
83 };
84
85 struct sdhci_sprd_phy_cfg {
86 const char *property;
87 u8 timing;
88 };
89
90 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
91 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
92 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
93 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
94 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
95 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
96 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
97 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
98 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
99 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
100 };
101
102 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
103
sdhci_sprd_init_config(struct sdhci_host * host)104 static void sdhci_sprd_init_config(struct sdhci_host *host)
105 {
106 u16 val;
107
108 /* set dll backup mode */
109 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
110 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
111 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
112 }
113
sdhci_sprd_readl(struct sdhci_host * host,int reg)114 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
115 {
116 if (unlikely(reg == SDHCI_MAX_CURRENT))
117 return SDHCI_SPRD_MAX_CUR;
118
119 return readl_relaxed(host->ioaddr + reg);
120 }
121
sdhci_sprd_writel(struct sdhci_host * host,u32 val,int reg)122 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
123 {
124 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
125 if (unlikely(reg == SDHCI_MAX_CURRENT))
126 return;
127
128 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
129 val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
130
131 writel_relaxed(val, host->ioaddr + reg);
132 }
133
sdhci_sprd_writew(struct sdhci_host * host,u16 val,int reg)134 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
135 {
136 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
137 if (unlikely(reg == SDHCI_BLOCK_COUNT))
138 return;
139
140 writew_relaxed(val, host->ioaddr + reg);
141 }
142
sdhci_sprd_writeb(struct sdhci_host * host,u8 val,int reg)143 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
144 {
145 /*
146 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
147 * standard specification, sdhci_reset() write this register directly
148 * without checking other reserved bits, that will clear BIT(3) which
149 * is defined as hardware reset on Spreadtrum's platform and clearing
150 * it by mistake will lead the card not work. So here we need to work
151 * around it.
152 */
153 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
154 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
155 val |= SDHCI_HW_RESET_CARD;
156 }
157
158 writeb_relaxed(val, host->ioaddr + reg);
159 }
160
sdhci_sprd_sd_clk_off(struct sdhci_host * host)161 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
162 {
163 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
164
165 ctrl &= ~SDHCI_CLOCK_CARD_EN;
166 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
167 }
168
sdhci_sprd_sd_clk_on(struct sdhci_host * host)169 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
170 {
171 u16 ctrl;
172
173 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
174 ctrl |= SDHCI_CLOCK_CARD_EN;
175 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
176 }
177
178 static inline void
sdhci_sprd_set_dll_invert(struct sdhci_host * host,u32 mask,bool en)179 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
180 {
181 u32 dll_dly_offset;
182
183 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
184 if (en)
185 dll_dly_offset |= mask;
186 else
187 dll_dly_offset &= ~mask;
188 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
189 }
190
sdhci_sprd_calc_div(u32 base_clk,u32 clk)191 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
192 {
193 u32 div;
194
195 /* select 2x clock source */
196 if (base_clk <= clk * 2)
197 return 0;
198
199 div = (u32) (base_clk / (clk * 2));
200
201 if ((base_clk / div) > (clk * 2))
202 div++;
203
204 if (div > SDHCI_SPRD_CLK_MAX_DIV)
205 div = SDHCI_SPRD_CLK_MAX_DIV;
206
207 if (div % 2)
208 div = (div + 1) / 2;
209 else
210 div = div / 2;
211
212 return div;
213 }
214
_sdhci_sprd_set_clock(struct sdhci_host * host,unsigned int clk)215 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
216 unsigned int clk)
217 {
218 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
219 u32 div, val, mask;
220
221 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
222
223 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
224 div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
225 sdhci_enable_clk(host, div);
226
227 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
228 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
229 /* Enable CLK_AUTO when the clock is greater than 400K. */
230 if (clk > 400000) {
231 if (mask != (val & mask)) {
232 val |= mask;
233 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
234 }
235 } else {
236 if (val & mask) {
237 val &= ~mask;
238 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
239 }
240 }
241 }
242
sdhci_sprd_enable_phy_dll(struct sdhci_host * host)243 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
244 {
245 u32 tmp;
246
247 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
248 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
249 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
250 /* wait 1ms */
251 usleep_range(1000, 1250);
252
253 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
254 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
255 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
256 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
257 /* wait 1ms */
258 usleep_range(1000, 1250);
259
260 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
261 tmp |= SDHCI_SPRD_DLL_EN;
262 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
263 /* wait 1ms */
264 usleep_range(1000, 1250);
265 }
266
sdhci_sprd_set_clock(struct sdhci_host * host,unsigned int clock)267 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
268 {
269 bool en = false, clk_changed = false;
270
271 if (clock == 0) {
272 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
273 } else if (clock != host->clock) {
274 sdhci_sprd_sd_clk_off(host);
275 _sdhci_sprd_set_clock(host, clock);
276
277 if (clock <= 400000)
278 en = true;
279 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
280 SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
281 clk_changed = true;
282 } else {
283 _sdhci_sprd_set_clock(host, clock);
284 }
285
286 /*
287 * According to the Spreadtrum SD host specification, when we changed
288 * the clock to be more than 52M, we should enable the PHY DLL which
289 * is used to track the clock frequency to make the clock work more
290 * stable. Otherwise deviation may occur of the higher clock.
291 */
292 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
293 sdhci_sprd_enable_phy_dll(host);
294 }
295
sdhci_sprd_get_max_clock(struct sdhci_host * host)296 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
297 {
298 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
299
300 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
301 }
302
sdhci_sprd_get_min_clock(struct sdhci_host * host)303 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
304 {
305 return 100000;
306 }
307
sdhci_sprd_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)308 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
309 unsigned int timing)
310 {
311 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
312 struct mmc_host *mmc = host->mmc;
313 u32 *p = sprd_host->phy_delay;
314 u16 ctrl_2;
315
316 if (timing == host->timing)
317 return;
318
319 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
320 /* Select Bus Speed Mode for host */
321 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
322 switch (timing) {
323 case MMC_TIMING_UHS_SDR12:
324 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
325 break;
326 case MMC_TIMING_MMC_HS:
327 case MMC_TIMING_SD_HS:
328 case MMC_TIMING_UHS_SDR25:
329 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
330 break;
331 case MMC_TIMING_UHS_SDR50:
332 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
333 break;
334 case MMC_TIMING_UHS_SDR104:
335 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
336 break;
337 case MMC_TIMING_UHS_DDR50:
338 case MMC_TIMING_MMC_DDR52:
339 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
340 break;
341 case MMC_TIMING_MMC_HS200:
342 ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
343 break;
344 case MMC_TIMING_MMC_HS400:
345 ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
346 break;
347 default:
348 break;
349 }
350
351 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
352
353 if (!mmc->ios.enhanced_strobe)
354 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
355 }
356
sdhci_sprd_hw_reset(struct sdhci_host * host)357 static void sdhci_sprd_hw_reset(struct sdhci_host *host)
358 {
359 int val;
360
361 /*
362 * Note: don't use sdhci_writeb() API here since it is redirected to
363 * sdhci_sprd_writeb() in which we have a workaround for
364 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
365 * not be cleared.
366 */
367 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
368 val &= ~SDHCI_HW_RESET_CARD;
369 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
370 /* wait for 10 us */
371 usleep_range(10, 20);
372
373 val |= SDHCI_HW_RESET_CARD;
374 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
375 usleep_range(300, 500);
376 }
377
sdhci_sprd_get_max_timeout_count(struct sdhci_host * host)378 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
379 {
380 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
381 return 1 << 31;
382 }
383
sdhci_sprd_get_ro(struct sdhci_host * host)384 static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
385 {
386 return 0;
387 }
388
sdhci_sprd_request_done(struct sdhci_host * host,struct mmc_request * mrq)389 static void sdhci_sprd_request_done(struct sdhci_host *host,
390 struct mmc_request *mrq)
391 {
392 /* Validate if the request was from software queue firstly. */
393 if (mmc_hsq_finalize_request(host->mmc, mrq))
394 return;
395
396 mmc_request_done(host->mmc, mrq);
397 }
398
399 static struct sdhci_ops sdhci_sprd_ops = {
400 .read_l = sdhci_sprd_readl,
401 .write_l = sdhci_sprd_writel,
402 .write_w = sdhci_sprd_writew,
403 .write_b = sdhci_sprd_writeb,
404 .set_clock = sdhci_sprd_set_clock,
405 .get_max_clock = sdhci_sprd_get_max_clock,
406 .get_min_clock = sdhci_sprd_get_min_clock,
407 .set_bus_width = sdhci_set_bus_width,
408 .reset = sdhci_reset,
409 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
410 .hw_reset = sdhci_sprd_hw_reset,
411 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
412 .get_ro = sdhci_sprd_get_ro,
413 .request_done = sdhci_sprd_request_done,
414 };
415
sdhci_sprd_check_auto_cmd23(struct mmc_host * mmc,struct mmc_request * mrq)416 static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc,
417 struct mmc_request *mrq)
418 {
419 struct sdhci_host *host = mmc_priv(mmc);
420 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
421
422 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
423
424 /*
425 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
426 * block count register which doesn't support stuff bits of
427 * CMD23 argument on Spreadtrum's sd host controller.
428 */
429 if (host->version >= SDHCI_SPEC_410 &&
430 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
431 (host->flags & SDHCI_AUTO_CMD23))
432 host->flags &= ~SDHCI_AUTO_CMD23;
433 }
434
sdhci_sprd_request(struct mmc_host * mmc,struct mmc_request * mrq)435 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
436 {
437 sdhci_sprd_check_auto_cmd23(mmc, mrq);
438
439 sdhci_request(mmc, mrq);
440 }
441
sdhci_sprd_request_atomic(struct mmc_host * mmc,struct mmc_request * mrq)442 static int sdhci_sprd_request_atomic(struct mmc_host *mmc,
443 struct mmc_request *mrq)
444 {
445 sdhci_sprd_check_auto_cmd23(mmc, mrq);
446
447 return sdhci_request_atomic(mmc, mrq);
448 }
449
sdhci_sprd_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)450 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
451 {
452 struct sdhci_host *host = mmc_priv(mmc);
453 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
454 int ret;
455
456 if (!IS_ERR(mmc->supply.vqmmc)) {
457 ret = mmc_regulator_set_vqmmc(mmc, ios);
458 if (ret < 0) {
459 pr_err("%s: Switching signalling voltage failed\n",
460 mmc_hostname(mmc));
461 return ret;
462 }
463 }
464
465 if (IS_ERR(sprd_host->pinctrl))
466 goto reset;
467
468 switch (ios->signal_voltage) {
469 case MMC_SIGNAL_VOLTAGE_180:
470 ret = pinctrl_select_state(sprd_host->pinctrl,
471 sprd_host->pins_uhs);
472 if (ret) {
473 pr_err("%s: failed to select uhs pin state\n",
474 mmc_hostname(mmc));
475 return ret;
476 }
477 break;
478
479 default:
480 fallthrough;
481 case MMC_SIGNAL_VOLTAGE_330:
482 ret = pinctrl_select_state(sprd_host->pinctrl,
483 sprd_host->pins_default);
484 if (ret) {
485 pr_err("%s: failed to select default pin state\n",
486 mmc_hostname(mmc));
487 return ret;
488 }
489 break;
490 }
491
492 /* Wait for 300 ~ 500 us for pin state stable */
493 usleep_range(300, 500);
494
495 reset:
496 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
497
498 return 0;
499 }
500
sdhci_sprd_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)501 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
502 struct mmc_ios *ios)
503 {
504 struct sdhci_host *host = mmc_priv(mmc);
505 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
506 u32 *p = sprd_host->phy_delay;
507 u16 ctrl_2;
508
509 if (!ios->enhanced_strobe)
510 return;
511
512 sdhci_sprd_sd_clk_off(host);
513
514 /* Set HS400 enhanced strobe mode */
515 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
516 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
517 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
518 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
519
520 sdhci_sprd_sd_clk_on(host);
521
522 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
523 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
524 SDHCI_SPRD_REG_32_DLL_DLY);
525 }
526
sdhci_sprd_phy_param_parse(struct sdhci_sprd_host * sprd_host,struct device_node * np)527 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
528 struct device_node *np)
529 {
530 u32 *p = sprd_host->phy_delay;
531 int ret, i, index;
532 u32 val[4];
533
534 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
535 ret = of_property_read_u32_array(np,
536 sdhci_sprd_phy_cfgs[i].property, val, 4);
537 if (ret)
538 continue;
539
540 index = sdhci_sprd_phy_cfgs[i].timing;
541 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
542 }
543 }
544
545 static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
546 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
547 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
548 SDHCI_QUIRK_MISSING_CAPS,
549 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
550 SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
551 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
552 .ops = &sdhci_sprd_ops,
553 };
554
sdhci_sprd_probe(struct platform_device * pdev)555 static int sdhci_sprd_probe(struct platform_device *pdev)
556 {
557 struct sdhci_host *host;
558 struct sdhci_sprd_host *sprd_host;
559 struct mmc_hsq *hsq;
560 struct clk *clk;
561 int ret = 0;
562
563 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
564 if (IS_ERR(host))
565 return PTR_ERR(host);
566
567 host->dma_mask = DMA_BIT_MASK(64);
568 pdev->dev.dma_mask = &host->dma_mask;
569 host->mmc_host_ops.request = sdhci_sprd_request;
570 host->mmc_host_ops.hs400_enhanced_strobe =
571 sdhci_sprd_hs400_enhanced_strobe;
572 /*
573 * We can not use the standard ops to change and detect the voltage
574 * signal for Spreadtrum SD host controller, since our voltage regulator
575 * for I/O is fixed in hardware, that means we do not need control
576 * the standard SD host controller to change the I/O voltage.
577 */
578 host->mmc_host_ops.start_signal_voltage_switch =
579 sdhci_sprd_voltage_switch;
580
581 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
582 MMC_CAP_WAIT_WHILE_BUSY;
583
584 ret = mmc_of_parse(host->mmc);
585 if (ret)
586 goto pltfm_free;
587
588 if (!mmc_card_is_removable(host->mmc))
589 host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic;
590 else
591 host->always_defer_done = true;
592
593 sprd_host = TO_SPRD_HOST(host);
594 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
595
596 sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
597 if (!IS_ERR(sprd_host->pinctrl)) {
598 sprd_host->pins_uhs =
599 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
600 if (IS_ERR(sprd_host->pins_uhs)) {
601 ret = PTR_ERR(sprd_host->pins_uhs);
602 goto pltfm_free;
603 }
604
605 sprd_host->pins_default =
606 pinctrl_lookup_state(sprd_host->pinctrl, "default");
607 if (IS_ERR(sprd_host->pins_default)) {
608 ret = PTR_ERR(sprd_host->pins_default);
609 goto pltfm_free;
610 }
611 }
612
613 clk = devm_clk_get(&pdev->dev, "sdio");
614 if (IS_ERR(clk)) {
615 ret = PTR_ERR(clk);
616 goto pltfm_free;
617 }
618 sprd_host->clk_sdio = clk;
619 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
620 if (!sprd_host->base_rate)
621 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
622
623 clk = devm_clk_get(&pdev->dev, "enable");
624 if (IS_ERR(clk)) {
625 ret = PTR_ERR(clk);
626 goto pltfm_free;
627 }
628 sprd_host->clk_enable = clk;
629
630 clk = devm_clk_get(&pdev->dev, "2x_enable");
631 if (!IS_ERR(clk))
632 sprd_host->clk_2x_enable = clk;
633
634 ret = clk_prepare_enable(sprd_host->clk_sdio);
635 if (ret)
636 goto pltfm_free;
637
638 ret = clk_prepare_enable(sprd_host->clk_enable);
639 if (ret)
640 goto clk_disable;
641
642 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
643 if (ret)
644 goto clk_disable2;
645
646 sdhci_sprd_init_config(host);
647 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
648 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
649 SDHCI_VENDOR_VER_SHIFT);
650
651 pm_runtime_get_noresume(&pdev->dev);
652 pm_runtime_set_active(&pdev->dev);
653 pm_runtime_enable(&pdev->dev);
654 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
655 pm_runtime_use_autosuspend(&pdev->dev);
656 pm_suspend_ignore_children(&pdev->dev, 1);
657
658 sdhci_enable_v4_mode(host);
659
660 /*
661 * Supply the existing CAPS, but clear the UHS-I modes. This
662 * will allow these modes to be specified only by device
663 * tree properties through mmc_of_parse().
664 */
665 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
666 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
667 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
668 SDHCI_SUPPORT_DDR50);
669
670 ret = sdhci_setup_host(host);
671 if (ret)
672 goto pm_runtime_disable;
673
674 sprd_host->flags = host->flags;
675
676 hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
677 if (!hsq) {
678 ret = -ENOMEM;
679 goto err_cleanup_host;
680 }
681
682 ret = mmc_hsq_init(hsq, host->mmc);
683 if (ret)
684 goto err_cleanup_host;
685
686 ret = __sdhci_add_host(host);
687 if (ret)
688 goto err_cleanup_host;
689
690 pm_runtime_mark_last_busy(&pdev->dev);
691 pm_runtime_put_autosuspend(&pdev->dev);
692
693 return 0;
694
695 err_cleanup_host:
696 sdhci_cleanup_host(host);
697
698 pm_runtime_disable:
699 pm_runtime_put_noidle(&pdev->dev);
700 pm_runtime_disable(&pdev->dev);
701 pm_runtime_set_suspended(&pdev->dev);
702
703 clk_disable_unprepare(sprd_host->clk_2x_enable);
704
705 clk_disable2:
706 clk_disable_unprepare(sprd_host->clk_enable);
707
708 clk_disable:
709 clk_disable_unprepare(sprd_host->clk_sdio);
710
711 pltfm_free:
712 sdhci_pltfm_free(pdev);
713 return ret;
714 }
715
sdhci_sprd_remove(struct platform_device * pdev)716 static int sdhci_sprd_remove(struct platform_device *pdev)
717 {
718 struct sdhci_host *host = platform_get_drvdata(pdev);
719 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
720
721 sdhci_remove_host(host, 0);
722
723 clk_disable_unprepare(sprd_host->clk_sdio);
724 clk_disable_unprepare(sprd_host->clk_enable);
725 clk_disable_unprepare(sprd_host->clk_2x_enable);
726
727 sdhci_pltfm_free(pdev);
728
729 return 0;
730 }
731
732 static const struct of_device_id sdhci_sprd_of_match[] = {
733 { .compatible = "sprd,sdhci-r11", },
734 { }
735 };
736 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
737
738 #ifdef CONFIG_PM
sdhci_sprd_runtime_suspend(struct device * dev)739 static int sdhci_sprd_runtime_suspend(struct device *dev)
740 {
741 struct sdhci_host *host = dev_get_drvdata(dev);
742 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
743
744 mmc_hsq_suspend(host->mmc);
745 sdhci_runtime_suspend_host(host);
746
747 clk_disable_unprepare(sprd_host->clk_sdio);
748 clk_disable_unprepare(sprd_host->clk_enable);
749 clk_disable_unprepare(sprd_host->clk_2x_enable);
750
751 return 0;
752 }
753
sdhci_sprd_runtime_resume(struct device * dev)754 static int sdhci_sprd_runtime_resume(struct device *dev)
755 {
756 struct sdhci_host *host = dev_get_drvdata(dev);
757 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
758 int ret;
759
760 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
761 if (ret)
762 return ret;
763
764 ret = clk_prepare_enable(sprd_host->clk_enable);
765 if (ret)
766 goto clk_2x_disable;
767
768 ret = clk_prepare_enable(sprd_host->clk_sdio);
769 if (ret)
770 goto clk_disable;
771
772 sdhci_runtime_resume_host(host, 1);
773 mmc_hsq_resume(host->mmc);
774
775 return 0;
776
777 clk_disable:
778 clk_disable_unprepare(sprd_host->clk_enable);
779
780 clk_2x_disable:
781 clk_disable_unprepare(sprd_host->clk_2x_enable);
782
783 return ret;
784 }
785 #endif
786
787 static const struct dev_pm_ops sdhci_sprd_pm_ops = {
788 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
789 pm_runtime_force_resume)
790 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
791 sdhci_sprd_runtime_resume, NULL)
792 };
793
794 static struct platform_driver sdhci_sprd_driver = {
795 .probe = sdhci_sprd_probe,
796 .remove = sdhci_sprd_remove,
797 .driver = {
798 .name = "sdhci_sprd_r11",
799 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
800 .of_match_table = of_match_ptr(sdhci_sprd_of_match),
801 .pm = &sdhci_sprd_pm_ops,
802 },
803 };
804 module_platform_driver(sdhci_sprd_driver);
805
806 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
807 MODULE_LICENSE("GPL v2");
808 MODULE_ALIAS("platform:sdhci-sprd-r11");
809