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Searched refs:SIRFSOC_INT_RISC_MASK0 (Results 1 – 1 of 1) sorted by relevance

/drivers/irqchip/
Dirq-sirfsoc.c19 #define SIRFSOC_INT_RISC_MASK0 0x0018 macro
54 ct->regs.mask = SIRFSOC_INT_RISC_MASK0; in sirfsoc_alloc_gc()
81 writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_init()
103 sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_suspend()
115 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_resume()