Searched refs:TIMER1 (Results 1 – 6 of 6) sorted by relevance
| /drivers/staging/rtl8712/ |
| D | rtl8712_gp_regdef.h | 18 #define TIMER1 (RTL8712_GP_ + 0x04) macro
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| /drivers/pinctrl/ |
| D | pinctrl-lpc18xx.c | 295 LPC_P(5,0, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
296 LPC_P(5,1, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
297 LPC_P(5,2, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
298 LPC_P(5,3, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
299 LPC_P(5,4, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
300 LPC_P(5,5, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
301 LPC_P(5,6, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
302 LPC_P(5,7, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
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| /drivers/clocksource/ |
| D | Kconfig | 165 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
166 where TIMER0 serves as clockevent and TIMER1 serves as clocksource.
311 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
313 TIMER0 serves as clockevent while TIMER1 provides clocksource.
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| /drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 267 LPC32XX_CLK_DEFINE(TIMER1, "timer1", 0x0, LPC32XX_CLK_PERIPH),
1258 LPC32XX_DEFINE_GATE(TIMER1, TIMCLK_CTRL1, 3, 0),
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| /drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| D | reg.h | 225 #define TIMER1 0x02E8 macro
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| /drivers/tty/ |
| D | synclinkmp.c | 382 #define TIMER1 0x08 macro
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