| /drivers/phy/rockchip/ |
| D | phy-rockchip-inno-hdmi.c | 24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
37 #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
39 #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
54 #define RK3228_PRE_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
56 #define RK3228_PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
58 #define RK3228_PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
60 #define RK3228_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
64 #define RK3228_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
66 #define RK3228_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
69 #define RK3228_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
[all …]
|
| D | phy-rockchip-inno-dsidphy.c | 25 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
50 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
51 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
64 #define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5)
66 #define REG_PREDIV(x) UPDATE(x, 4, 0)
69 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
72 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
74 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
77 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
79 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
[all …]
|
| /drivers/gpu/drm/nouveau/dispnv50/ |
| D | core507d.c | 49 PUSH_MTHD(push, NV507D, UPDATE, interlock[NV50_DISP_INTERLOCK_BASE] | in core507d_update()
51 NVDEF(NV507D, UPDATE, NOT_DRIVER_FRIENDLY, FALSE) | in core507d_update()
52 NVDEF(NV507D, UPDATE, NOT_DRIVER_UNFRIENDLY, FALSE) | in core507d_update()
53 NVDEF(NV507D, UPDATE, INHIBIT_INTERRUPTS, FALSE), in core507d_update()
|
| D | corec37d.c | 69 PUSH_MTHD(push, NVC37D, UPDATE, 0x00000001 | in corec37d_update()
70 NVDEF(NVC37D, UPDATE, SPECIAL_HANDLING, NONE) | in corec37d_update()
71 NVDEF(NVC37D, UPDATE, INHIBIT_INTERRUPTS, FALSE)); in corec37d_update()
|
| D | wimmc37b.c | 40 PUSH_MTHD(push, NVC37B, UPDATE, 0x00000001 | in wimmc37b_update()
41 NVVAL(NVC37B, UPDATE, INTERLOCK_WITH_WINDOW, in wimmc37b_update()
|
| D | curs507a.c | 52 NVIF_WR32(user, NV507A, UPDATE, in curs507a_update()
53 NVDEF(NV507A, UPDATE, INTERLOCK_WITH_CORE, DISABLE)); in curs507a_update()
|
| D | cursc37a.c | 33 NVIF_WR32(user, NVC37A, UPDATE, 0x00000001); in cursc37a_update()
|
| D | wndwc37e.c | 286 PUSH_MTHD(push, NVC37E, UPDATE, 0x00000001 | in wndwc37e_update()
287 NVVAL(NVC37E, UPDATE, INTERLOCK_WITH_WIN_IMM, in wndwc37e_update()
|
| D | base507c.c | 46 PUSH_MTHD(push, NV507C, UPDATE, interlock[NV50_DISP_INTERLOCK_CORE]); in base507c_update()
|
| /drivers/gpu/drm/i915/gem/ |
| D | i915_gem_execbuffer.c | 60 #define UPDATE PIN_OFFSET_FIXED macro
611 entry->offset = vma->node.start | UPDATE; in eb_reserve_vma()
903 entry->offset = vma->node.start | UPDATE; in eb_validate_vmas()
1572 return target->node.start | UPDATE; in relocate_entry()
1743 offset = gen8_canonical_addr(offset & ~UPDATE); in eb_relocate_vma()
3347 if (!(exec2_list[i].offset & UPDATE)) in i915_gem_execbuffer_ioctl()
3426 if (!(exec2_list[i].offset & UPDATE)) in i915_gem_execbuffer2_ioctl()
|
| /drivers/net/wireless/ath/ath9k/ |
| D | htc.h | 413 UPDATE, /* update pending */ enumerator
|
| D | beacon.c | 486 if (sc->beacon.updateslot == UPDATE) { in ath9k_beacon_tasklet()
|
| D | ath9k.h | 700 UPDATE, /* update pending */ enumerator
|
| D | htc_drv_main.c | 1603 priv->beacon.updateslot = UPDATE; in ath9k_htc_bss_info_changed()
|
| D | main.c | 1926 sc->beacon.updateslot = UPDATE; in ath9k_bss_info_changed()
|
| /drivers/crypto/caam/ |
| D | caamalg_qi2.c | 3041 UPDATE = 0, enumerator
3140 flc = &ctx->flc[UPDATE]; in ahash_set_sh_desc()
3145 dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE], in ahash_set_sh_desc()
3607 req_ctx->flc = &ctx->flc[UPDATE]; in ahash_update_ctx()
3608 req_ctx->flc_dma = ctx->flc_dma[UPDATE]; in ahash_update_ctx()
|