1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 #include "vc4_hdmi.h"
10 #include "vc4_regs.h"
11 #include "vc4_hdmi_regs.h"
12
13 #define VC4_HDMI_TX_PHY_RESET_CTL_PLL_RESETB BIT(5)
14 #define VC4_HDMI_TX_PHY_RESET_CTL_PLLDIV_RESETB BIT(4)
15 #define VC4_HDMI_TX_PHY_RESET_CTL_TX_CK_RESET BIT(3)
16 #define VC4_HDMI_TX_PHY_RESET_CTL_TX_2_RESET BIT(2)
17 #define VC4_HDMI_TX_PHY_RESET_CTL_TX_1_RESET BIT(1)
18 #define VC4_HDMI_TX_PHY_RESET_CTL_TX_0_RESET BIT(0)
19
20 #define VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN BIT(4)
21
22 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_SHIFT 29
23 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_MASK VC4_MASK(31, 29)
24 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_SHIFT 24
25 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_MASK VC4_MASK(28, 24)
26 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_SHIFT 21
27 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_MASK VC4_MASK(23, 21)
28 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_SHIFT 16
29 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_MASK VC4_MASK(20, 16)
30 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_SHIFT 13
31 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_MASK VC4_MASK(15, 13)
32 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_SHIFT 8
33 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_MASK VC4_MASK(12, 8)
34 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_SHIFT 5
35 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_MASK VC4_MASK(7, 5)
36 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_SHIFT 0
37 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK VC4_MASK(4, 0)
38
39 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_SHIFT 15
40 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_MASK VC4_MASK(19, 15)
41 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_SHIFT 10
42 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_MASK VC4_MASK(14, 10)
43 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0_SHIFT 5
44 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0_MASK VC4_MASK(9, 5)
45 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_SHIFT 0
46 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_MASK VC4_MASK(4, 0)
47
48 #define VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN_SHIFT 16
49 #define VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN_MASK VC4_MASK(19, 16)
50 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2_SHIFT 12
51 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2_MASK VC4_MASK(15, 12)
52 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1_SHIFT 8
53 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1_MASK VC4_MASK(11, 8)
54 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_SHIFT 4
55 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_MASK VC4_MASK(7, 4)
56 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_SHIFT 0
57 #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_MASK VC4_MASK(3, 0)
58
59 #define VC4_HDMI_TX_PHY_CTL_3_RP_SHIFT 17
60 #define VC4_HDMI_TX_PHY_CTL_3_RP_MASK VC4_MASK(19, 17)
61 #define VC4_HDMI_TX_PHY_CTL_3_RZ_SHIFT 12
62 #define VC4_HDMI_TX_PHY_CTL_3_RZ_MASK VC4_MASK(16, 12)
63 #define VC4_HDMI_TX_PHY_CTL_3_CP1_SHIFT 10
64 #define VC4_HDMI_TX_PHY_CTL_3_CP1_MASK VC4_MASK(11, 10)
65 #define VC4_HDMI_TX_PHY_CTL_3_CP_SHIFT 8
66 #define VC4_HDMI_TX_PHY_CTL_3_CP_MASK VC4_MASK(9, 8)
67 #define VC4_HDMI_TX_PHY_CTL_3_CZ_SHIFT 6
68 #define VC4_HDMI_TX_PHY_CTL_3_CZ_MASK VC4_MASK(7, 6)
69 #define VC4_HDMI_TX_PHY_CTL_3_ICP_SHIFT 0
70 #define VC4_HDMI_TX_PHY_CTL_3_ICP_MASK VC4_MASK(5, 0)
71
72 #define VC4_HDMI_TX_PHY_PLL_CTL_0_MASH11_MODE BIT(13)
73 #define VC4_HDMI_TX_PHY_PLL_CTL_0_VC_RANGE_EN BIT(12)
74 #define VC4_HDMI_TX_PHY_PLL_CTL_0_EMULATE_VC_LOW BIT(11)
75 #define VC4_HDMI_TX_PHY_PLL_CTL_0_EMULATE_VC_HIGH BIT(10)
76 #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL_SHIFT 9
77 #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL_MASK VC4_MASK(9, 9)
78 #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_FB_DIV2 BIT(8)
79 #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_POST_DIV2 BIT(7)
80 #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_CONT_EN BIT(6)
81 #define VC4_HDMI_TX_PHY_PLL_CTL_0_ENA_VCO_CLK BIT(5)
82
83 #define VC4_HDMI_TX_PHY_PLL_CTL_1_CPP_SHIFT 16
84 #define VC4_HDMI_TX_PHY_PLL_CTL_1_CPP_MASK VC4_MASK(27, 16)
85 #define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY_SHIFT 14
86 #define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY_MASK VC4_MASK(15, 14)
87 #define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_ENABLE BIT(13)
88 #define VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL_SHIFT 11
89 #define VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL_MASK VC4_MASK(12, 11)
90
91 #define VC4_HDMI_TX_PHY_CLK_DIV_VCO_SHIFT 8
92 #define VC4_HDMI_TX_PHY_CLK_DIV_VCO_MASK VC4_MASK(15, 8)
93
94 #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_SHIFT 0
95 #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_MASK VC4_MASK(3, 0)
96
97 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL_MASK VC4_MASK(13, 12)
98 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL_SHIFT 12
99 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL_MASK VC4_MASK(9, 8)
100 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL_SHIFT 8
101 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_MASK VC4_MASK(5, 4)
102 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_SHIFT 4
103 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_MASK VC4_MASK(1, 0)
104 #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_SHIFT 0
105
106 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_MASK VC4_MASK(27, 0)
107 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_SHIFT 0
108
109 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_MASK VC4_MASK(27, 0)
110 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_SHIFT 0
111
112 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD_MASK VC4_MASK(31, 16)
113 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD_SHIFT 16
114 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_MASK VC4_MASK(15, 0)
115 #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_SHIFT 0
116
117 #define VC4_HDMI_RM_CONTROL_EN_FREEZE_COUNTERS BIT(19)
118 #define VC4_HDMI_RM_CONTROL_EN_LOAD_INTEGRATOR BIT(17)
119 #define VC4_HDMI_RM_CONTROL_FREE_RUN BIT(4)
120
121 #define VC4_HDMI_RM_OFFSET_ONLY BIT(31)
122 #define VC4_HDMI_RM_OFFSET_OFFSET_SHIFT 0
123 #define VC4_HDMI_RM_OFFSET_OFFSET_MASK VC4_MASK(30, 0)
124
125 #define VC4_HDMI_RM_FORMAT_SHIFT_SHIFT 24
126 #define VC4_HDMI_RM_FORMAT_SHIFT_MASK VC4_MASK(25, 24)
127
128 #define OSCILLATOR_FREQUENCY 54000000
129
vc4_hdmi_phy_init(struct vc4_hdmi * vc4_hdmi,struct drm_display_mode * mode)130 void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode *mode)
131 {
132 /* PHY should be in reset, like
133 * vc4_hdmi_encoder_disable() does.
134 */
135
136 HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);
137 HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
138 }
139
vc4_hdmi_phy_disable(struct vc4_hdmi * vc4_hdmi)140 void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)
141 {
142 HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);
143 }
144
vc4_hdmi_phy_rng_enable(struct vc4_hdmi * vc4_hdmi)145 void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi)
146 {
147 HDMI_WRITE(HDMI_TX_PHY_CTL_0,
148 HDMI_READ(HDMI_TX_PHY_CTL_0) &
149 ~VC4_HDMI_TX_PHY_RNG_PWRDN);
150 }
151
vc4_hdmi_phy_rng_disable(struct vc4_hdmi * vc4_hdmi)152 void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi)
153 {
154 HDMI_WRITE(HDMI_TX_PHY_CTL_0,
155 HDMI_READ(HDMI_TX_PHY_CTL_0) |
156 VC4_HDMI_TX_PHY_RNG_PWRDN);
157 }
158
159 static unsigned long long
phy_get_vco_freq(unsigned long long clock,u8 * vco_sel,u8 * vco_div)160 phy_get_vco_freq(unsigned long long clock, u8 *vco_sel, u8 *vco_div)
161 {
162 unsigned long long vco_freq = clock;
163 unsigned int _vco_div = 0;
164 unsigned int _vco_sel = 0;
165
166 while (vco_freq < 3000000000ULL) {
167 _vco_div++;
168 vco_freq = clock * _vco_div * 10;
169 }
170
171 if (vco_freq > 4500000000ULL)
172 _vco_sel = 1;
173
174 *vco_sel = _vco_sel;
175 *vco_div = _vco_div;
176
177 return vco_freq;
178 }
179
phy_get_cp_current(unsigned long vco_freq)180 static u8 phy_get_cp_current(unsigned long vco_freq)
181 {
182 if (vco_freq < 3700000000ULL)
183 return 0x1c;
184
185 return 0x18;
186 }
187
phy_get_rm_offset(unsigned long long vco_freq)188 static u32 phy_get_rm_offset(unsigned long long vco_freq)
189 {
190 unsigned long long fref = OSCILLATOR_FREQUENCY;
191 u64 offset = 0;
192
193 /* RM offset is stored as 9.22 format */
194 offset = vco_freq * 2;
195 offset = offset << 22;
196 do_div(offset, fref);
197 offset >>= 2;
198
199 return offset;
200 }
201
phy_get_vco_gain(unsigned long long vco_freq)202 static u8 phy_get_vco_gain(unsigned long long vco_freq)
203 {
204 if (vco_freq < 3350000000ULL)
205 return 0xf;
206
207 if (vco_freq < 3700000000ULL)
208 return 0xc;
209
210 if (vco_freq < 4050000000ULL)
211 return 0x6;
212
213 if (vco_freq < 4800000000ULL)
214 return 0x5;
215
216 if (vco_freq < 5200000000ULL)
217 return 0x7;
218
219 return 0x2;
220 }
221
222 struct phy_lane_settings {
223 struct {
224 u8 preemphasis;
225 u8 main_driver;
226 } amplitude;
227
228 u8 res_sel_data;
229 u8 term_res_sel_data;
230 };
231
232 struct phy_settings {
233 unsigned long long min_rate;
234 unsigned long long max_rate;
235 struct phy_lane_settings channel[3];
236 struct phy_lane_settings clock;
237 };
238
239 static const struct phy_settings vc5_hdmi_phy_settings[] = {
240 {
241 0, 50000000,
242 {
243 {{0x0, 0x0A}, 0x12, 0x0},
244 {{0x0, 0x0A}, 0x12, 0x0},
245 {{0x0, 0x0A}, 0x12, 0x0}
246 },
247 {{0x0, 0x0A}, 0x18, 0x0},
248 },
249 {
250 50000001, 75000000,
251 {
252 {{0x0, 0x09}, 0x12, 0x0},
253 {{0x0, 0x09}, 0x12, 0x0},
254 {{0x0, 0x09}, 0x12, 0x0}
255 },
256 {{0x0, 0x0C}, 0x18, 0x3},
257 },
258 {
259 75000001, 165000000,
260 {
261 {{0x0, 0x09}, 0x12, 0x0},
262 {{0x0, 0x09}, 0x12, 0x0},
263 {{0x0, 0x09}, 0x12, 0x0}
264 },
265 {{0x0, 0x0C}, 0x18, 0x3},
266 },
267 {
268 165000001, 250000000,
269 {
270 {{0x0, 0x0F}, 0x12, 0x1},
271 {{0x0, 0x0F}, 0x12, 0x1},
272 {{0x0, 0x0F}, 0x12, 0x1}
273 },
274 {{0x0, 0x0C}, 0x18, 0x3},
275 },
276 {
277 250000001, 340000000,
278 {
279 {{0x2, 0x0D}, 0x12, 0x1},
280 {{0x2, 0x0D}, 0x12, 0x1},
281 {{0x2, 0x0D}, 0x12, 0x1}
282 },
283 {{0x0, 0x0C}, 0x18, 0xF},
284 },
285 {
286 340000001, 450000000,
287 {
288 {{0x0, 0x1B}, 0x12, 0xF},
289 {{0x0, 0x1B}, 0x12, 0xF},
290 {{0x0, 0x1B}, 0x12, 0xF}
291 },
292 {{0x0, 0x0A}, 0x12, 0xF},
293 },
294 {
295 450000001, 600000000,
296 {
297 {{0x0, 0x1C}, 0x12, 0xF},
298 {{0x0, 0x1C}, 0x12, 0xF},
299 {{0x0, 0x1C}, 0x12, 0xF}
300 },
301 {{0x0, 0x0B}, 0x13, 0xF},
302 },
303 };
304
phy_get_settings(unsigned long long tmds_rate)305 static const struct phy_settings *phy_get_settings(unsigned long long tmds_rate)
306 {
307 unsigned int count = ARRAY_SIZE(vc5_hdmi_phy_settings);
308 unsigned int i;
309
310 for (i = 0; i < count; i++) {
311 const struct phy_settings *s = &vc5_hdmi_phy_settings[i];
312
313 if (tmds_rate >= s->min_rate && tmds_rate <= s->max_rate)
314 return s;
315 }
316
317 /*
318 * If the pixel clock exceeds our max setting, try the max
319 * setting anyway.
320 */
321 return &vc5_hdmi_phy_settings[count - 1];
322 }
323
324 static const struct phy_lane_settings *
phy_get_channel_settings(enum vc4_hdmi_phy_channel chan,unsigned long long tmds_rate)325 phy_get_channel_settings(enum vc4_hdmi_phy_channel chan,
326 unsigned long long tmds_rate)
327 {
328 const struct phy_settings *settings = phy_get_settings(tmds_rate);
329
330 if (chan == PHY_LANE_CK)
331 return &settings->clock;
332
333 return &settings->channel[chan];
334 }
335
vc5_hdmi_reset_phy(struct vc4_hdmi * vc4_hdmi)336 static void vc5_hdmi_reset_phy(struct vc4_hdmi *vc4_hdmi)
337 {
338 HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0x0f);
339 HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL, BIT(10));
340 }
341
vc5_hdmi_phy_init(struct vc4_hdmi * vc4_hdmi,struct drm_display_mode * mode)342 void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode *mode)
343 {
344 const struct phy_lane_settings *chan0_settings, *chan1_settings, *chan2_settings, *clock_settings;
345 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
346 unsigned long long pixel_freq = mode->clock * 1000;
347 unsigned long long vco_freq;
348 unsigned char word_sel;
349 u8 vco_sel, vco_div;
350
351 vco_freq = phy_get_vco_freq(pixel_freq, &vco_sel, &vco_div);
352
353 vc5_hdmi_reset_phy(vc4_hdmi);
354
355 HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL,
356 VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN);
357
358 HDMI_WRITE(HDMI_TX_PHY_RESET_CTL,
359 HDMI_READ(HDMI_TX_PHY_RESET_CTL) &
360 ~VC4_HDMI_TX_PHY_RESET_CTL_TX_0_RESET &
361 ~VC4_HDMI_TX_PHY_RESET_CTL_TX_1_RESET &
362 ~VC4_HDMI_TX_PHY_RESET_CTL_TX_2_RESET &
363 ~VC4_HDMI_TX_PHY_RESET_CTL_TX_CK_RESET);
364
365 HDMI_WRITE(HDMI_RM_CONTROL,
366 HDMI_READ(HDMI_RM_CONTROL) |
367 VC4_HDMI_RM_CONTROL_EN_FREEZE_COUNTERS |
368 VC4_HDMI_RM_CONTROL_EN_LOAD_INTEGRATOR |
369 VC4_HDMI_RM_CONTROL_FREE_RUN);
370
371 HDMI_WRITE(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
372 (HDMI_READ(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1) &
373 ~VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_MASK) |
374 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT));
375
376 HDMI_WRITE(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
377 (HDMI_READ(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2) &
378 ~VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_MASK) |
379 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT));
380
381 HDMI_WRITE(HDMI_RM_OFFSET,
382 VC4_SET_FIELD(phy_get_rm_offset(vco_freq),
383 VC4_HDMI_RM_OFFSET_OFFSET) |
384 VC4_HDMI_RM_OFFSET_ONLY);
385
386 HDMI_WRITE(HDMI_TX_PHY_CLK_DIV,
387 VC4_SET_FIELD(vco_div, VC4_HDMI_TX_PHY_CLK_DIV_VCO));
388
389 HDMI_WRITE(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
390 VC4_SET_FIELD(0xe147, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD) |
391 VC4_SET_FIELD(0xe14, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD));
392
393 HDMI_WRITE(HDMI_TX_PHY_PLL_CTL_0,
394 VC4_HDMI_TX_PHY_PLL_CTL_0_ENA_VCO_CLK |
395 VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_CONT_EN |
396 VC4_HDMI_TX_PHY_PLL_CTL_0_MASH11_MODE |
397 VC4_SET_FIELD(vco_sel, VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL));
398
399 HDMI_WRITE(HDMI_TX_PHY_PLL_CTL_1,
400 HDMI_READ(HDMI_TX_PHY_PLL_CTL_1) |
401 VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_ENABLE |
402 VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL) |
403 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY) |
404 VC4_SET_FIELD(0x8a, VC4_HDMI_TX_PHY_PLL_CTL_1_CPP));
405
406 HDMI_WRITE(HDMI_RM_FORMAT,
407 HDMI_READ(HDMI_RM_FORMAT) |
408 VC4_SET_FIELD(2, VC4_HDMI_RM_FORMAT_SHIFT));
409
410 HDMI_WRITE(HDMI_TX_PHY_PLL_CFG,
411 HDMI_READ(HDMI_TX_PHY_PLL_CFG) |
412 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CFG_PDIV));
413
414 if (pixel_freq >= 340000000)
415 word_sel = 3;
416 else
417 word_sel = 0;
418 HDMI_WRITE(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, word_sel);
419
420 HDMI_WRITE(HDMI_TX_PHY_CTL_3,
421 VC4_SET_FIELD(phy_get_cp_current(vco_freq),
422 VC4_HDMI_TX_PHY_CTL_3_ICP) |
423 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_CTL_3_CP) |
424 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_CTL_3_CP1) |
425 VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_CTL_3_CZ) |
426 VC4_SET_FIELD(4, VC4_HDMI_TX_PHY_CTL_3_RP) |
427 VC4_SET_FIELD(6, VC4_HDMI_TX_PHY_CTL_3_RZ));
428
429 chan0_settings =
430 phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_0],
431 pixel_freq);
432 chan1_settings =
433 phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_1],
434 pixel_freq);
435 chan2_settings =
436 phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_2],
437 pixel_freq);
438 clock_settings =
439 phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_CK],
440 pixel_freq);
441
442 HDMI_WRITE(HDMI_TX_PHY_CTL_0,
443 VC4_SET_FIELD(chan0_settings->amplitude.preemphasis,
444 VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP) |
445 VC4_SET_FIELD(chan0_settings->amplitude.main_driver,
446 VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV) |
447 VC4_SET_FIELD(chan1_settings->amplitude.preemphasis,
448 VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP) |
449 VC4_SET_FIELD(chan1_settings->amplitude.main_driver,
450 VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV) |
451 VC4_SET_FIELD(chan2_settings->amplitude.preemphasis,
452 VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP) |
453 VC4_SET_FIELD(chan2_settings->amplitude.main_driver,
454 VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV) |
455 VC4_SET_FIELD(clock_settings->amplitude.preemphasis,
456 VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP) |
457 VC4_SET_FIELD(clock_settings->amplitude.main_driver,
458 VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV));
459
460 HDMI_WRITE(HDMI_TX_PHY_CTL_1,
461 HDMI_READ(HDMI_TX_PHY_CTL_1) |
462 VC4_SET_FIELD(chan0_settings->res_sel_data,
463 VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0) |
464 VC4_SET_FIELD(chan1_settings->res_sel_data,
465 VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1) |
466 VC4_SET_FIELD(chan2_settings->res_sel_data,
467 VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2) |
468 VC4_SET_FIELD(clock_settings->res_sel_data,
469 VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK));
470
471 HDMI_WRITE(HDMI_TX_PHY_CTL_2,
472 VC4_SET_FIELD(chan0_settings->term_res_sel_data,
473 VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0) |
474 VC4_SET_FIELD(chan1_settings->term_res_sel_data,
475 VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1) |
476 VC4_SET_FIELD(chan2_settings->term_res_sel_data,
477 VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2) |
478 VC4_SET_FIELD(clock_settings->term_res_sel_data,
479 VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK) |
480 VC4_SET_FIELD(phy_get_vco_gain(vco_freq),
481 VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN));
482
483 HDMI_WRITE(HDMI_TX_PHY_CHANNEL_SWAP,
484 VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_0],
485 VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL) |
486 VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_1],
487 VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL) |
488 VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_2],
489 VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL) |
490 VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_CK],
491 VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL));
492
493 HDMI_WRITE(HDMI_TX_PHY_RESET_CTL,
494 HDMI_READ(HDMI_TX_PHY_RESET_CTL) &
495 ~(VC4_HDMI_TX_PHY_RESET_CTL_PLL_RESETB |
496 VC4_HDMI_TX_PHY_RESET_CTL_PLLDIV_RESETB));
497
498 HDMI_WRITE(HDMI_TX_PHY_RESET_CTL,
499 HDMI_READ(HDMI_TX_PHY_RESET_CTL) |
500 VC4_HDMI_TX_PHY_RESET_CTL_PLL_RESETB |
501 VC4_HDMI_TX_PHY_RESET_CTL_PLLDIV_RESETB);
502 }
503
vc5_hdmi_phy_disable(struct vc4_hdmi * vc4_hdmi)504 void vc5_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)
505 {
506 vc5_hdmi_reset_phy(vc4_hdmi);
507 }
508
vc5_hdmi_phy_rng_enable(struct vc4_hdmi * vc4_hdmi)509 void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi)
510 {
511 HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL,
512 HDMI_READ(HDMI_TX_PHY_POWERDOWN_CTL) &
513 ~VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN);
514 }
515
vc5_hdmi_phy_rng_disable(struct vc4_hdmi * vc4_hdmi)516 void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi)
517 {
518 HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL,
519 HDMI_READ(HDMI_TX_PHY_POWERDOWN_CTL) |
520 VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN);
521 }
522