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Searched refs:VIU_SW_RESET_OSD1_AFBCD (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/meson/
Dmeson_osd_afbcd.c84 writel_relaxed(VIU_SW_RESET_OSD1_AFBCD, in meson_gxm_afbcd_reset()
Dmeson_registers.h141 #define VIU_SW_RESET_OSD1_AFBCD BIT(31) macro