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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Definitions for the new Marvell Yukon 2 driver.
4  */
5 #ifndef _SKY2_H
6 #define _SKY2_H
7 
8 #define ETH_JUMBO_MTU		9000	/* Maximum MTU supported */
9 
10 /* PCI config registers */
11 enum {
12 	PCI_DEV_REG1	= 0x40,
13 	PCI_DEV_REG2	= 0x44,
14 	PCI_DEV_STATUS  = 0x7c,
15 	PCI_DEV_REG3	= 0x80,
16 	PCI_DEV_REG4	= 0x84,
17 	PCI_DEV_REG5    = 0x88,
18 	PCI_CFG_REG_0	= 0x90,
19 	PCI_CFG_REG_1	= 0x94,
20 
21 	PSM_CONFIG_REG0  = 0x98,
22 	PSM_CONFIG_REG1	 = 0x9C,
23 	PSM_CONFIG_REG2  = 0x160,
24 	PSM_CONFIG_REG3  = 0x164,
25 	PSM_CONFIG_REG4  = 0x168,
26 
27 	PCI_LDO_CTRL    = 0xbc,
28 };
29 
30 /* Yukon-2 */
31 enum pci_dev_reg_1 {
32 	PCI_Y2_PIG_ENA	 = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 	PCI_Y2_DLL_DIS	 = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 	PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 	PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 	PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 	PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 	PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 	PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
40 
41 	PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit  9.. 8:	GPHY Link Trigger Timer */
42 	PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
43 	PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
44 	PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
45 };
46 
47 enum pci_dev_reg_2 {
48 	PCI_VPD_WR_THR	= 0xffL<<24,	/* Bit 31..24:	VPD Write Threshold */
49 	PCI_DEV_SEL	= 0x7fL<<17,	/* Bit 23..17:	EEPROM Device Select */
50 	PCI_VPD_ROM_SZ	= 7L<<14,	/* Bit 16..14:	VPD ROM Size	*/
51 
52 	PCI_PATCH_DIR	= 0xfL<<8,	/* Bit 11.. 8:	Ext Patches dir 3..0 */
53 	PCI_EXT_PATCHS	= 0xfL<<4,	/* Bit	7.. 4:	Extended Patches 3..0 */
54 	PCI_EN_DUMMY_RD	= 1<<3,		/* Enable Dummy Read */
55 	PCI_REV_DESC	= 1<<2,		/* Reverse Desc. Bytes */
56 
57 	PCI_USEDATA64	= 1<<0,		/* Use 64Bit Data bus ext */
58 };
59 
60 /*	PCI_OUR_REG_3		32 bit	Our Register 3 (Yukon-ECU only) */
61 enum pci_dev_reg_3 {
62 	P_CLK_ASF_REGS_DIS	= 1<<18,/* Disable Clock ASF (Yukon-Ext.) */
63 	P_CLK_COR_REGS_D0_DIS	= 1<<17,/* Disable Clock Core Regs D0 */
64 	P_CLK_MACSEC_DIS	= 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */
65 	P_CLK_PCI_REGS_D0_DIS	= 1<<16,/* Disable Clock PCI  Regs D0 */
66 	P_CLK_COR_YTB_ARB_DIS	= 1<<15,/* Disable Clock YTB  Arbiter */
67 	P_CLK_MAC_LNK1_D3_DIS	= 1<<14,/* Disable Clock MAC  Link1 D3 */
68 	P_CLK_COR_LNK1_D0_DIS	= 1<<13,/* Disable Clock Core Link1 D0 */
69 	P_CLK_MAC_LNK1_D0_DIS	= 1<<12,/* Disable Clock MAC  Link1 D0 */
70 	P_CLK_COR_LNK1_D3_DIS	= 1<<11,/* Disable Clock Core Link1 D3 */
71 	P_CLK_PCI_MST_ARB_DIS	= 1<<10,/* Disable Clock PCI  Master Arb. */
72 	P_CLK_COR_REGS_D3_DIS	= 1<<9,	/* Disable Clock Core Regs D3 */
73 	P_CLK_PCI_REGS_D3_DIS	= 1<<8,	/* Disable Clock PCI  Regs D3 */
74 	P_CLK_REF_LNK1_GM_DIS	= 1<<7,	/* Disable Clock Ref. Link1 GMAC */
75 	P_CLK_COR_LNK1_GM_DIS	= 1<<6,	/* Disable Clock Core Link1 GMAC */
76 	P_CLK_PCI_COMMON_DIS	= 1<<5,	/* Disable Clock PCI  Common */
77 	P_CLK_COR_COMMON_DIS	= 1<<4,	/* Disable Clock Core Common */
78 	P_CLK_PCI_LNK1_BMU_DIS	= 1<<3,	/* Disable Clock PCI  Link1 BMU */
79 	P_CLK_COR_LNK1_BMU_DIS	= 1<<2,	/* Disable Clock Core Link1 BMU */
80 	P_CLK_PCI_LNK1_BIU_DIS	= 1<<1,	/* Disable Clock PCI  Link1 BIU */
81 	P_CLK_COR_LNK1_BIU_DIS	= 1<<0,	/* Disable Clock Core Link1 BIU */
82 	PCIE_OUR3_WOL_D3_COLD_SET = P_CLK_ASF_REGS_DIS |
83 				    P_CLK_COR_REGS_D0_DIS |
84 				    P_CLK_COR_LNK1_D0_DIS |
85 				    P_CLK_MAC_LNK1_D0_DIS |
86 				    P_CLK_PCI_MST_ARB_DIS |
87 				    P_CLK_COR_COMMON_DIS |
88 				    P_CLK_COR_LNK1_BMU_DIS,
89 };
90 
91 /*	PCI_OUR_REG_4		32 bit	Our Register 4 (Yukon-ECU only) */
92 enum pci_dev_reg_4 {
93 				/* (Link Training & Status State Machine) */
94 	P_PEX_LTSSM_STAT_MSK	= 0x7fL<<25,	/* Bit 31..25:	PEX LTSSM Mask */
95 #define P_PEX_LTSSM_STAT(x)	((x << 25) & P_PEX_LTSSM_STAT_MSK)
96 	P_PEX_LTSSM_L1_STAT	= 0x34,
97 	P_PEX_LTSSM_DET_STAT	= 0x01,
98 	P_TIMER_VALUE_MSK	= 0xffL<<16,	/* Bit 23..16:	Timer Value Mask */
99 					/* (Active State Power Management) */
100 	P_FORCE_ASPM_REQUEST	= 1<<15, /* Force ASPM Request (A1 only) */
101 	P_ASPM_GPHY_LINK_DOWN	= 1<<14, /* GPHY Link Down (A1 only) */
102 	P_ASPM_INT_FIFO_EMPTY	= 1<<13, /* Internal FIFO Empty (A1 only) */
103 	P_ASPM_CLKRUN_REQUEST	= 1<<12, /* CLKRUN Request (A1 only) */
104 
105 	P_ASPM_FORCE_CLKREQ_ENA	= 1<<4,	/* Force CLKREQ Enable (A1b only) */
106 	P_ASPM_CLKREQ_PAD_CTL	= 1<<3,	/* CLKREQ PAD Control (A1 only) */
107 	P_ASPM_A1_MODE_SELECT	= 1<<2,	/* A1 Mode Select (A1 only) */
108 	P_CLK_GATE_PEX_UNIT_ENA	= 1<<1,	/* Enable Gate PEX Unit Clock */
109 	P_CLK_GATE_ROOT_COR_ENA	= 1<<0,	/* Enable Gate Root Core Clock */
110 	P_ASPM_CONTROL_MSK	= P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
111 				  | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
112 };
113 
114 /*	PCI_OUR_REG_5		32 bit	Our Register 5 (Yukon-ECU only) */
115 enum pci_dev_reg_5 {
116 					/* Bit 31..27:	for A3 & later */
117 	P_CTL_DIV_CORE_CLK_ENA	= 1<<31, /* Divide Core Clock Enable */
118 	P_CTL_SRESET_VMAIN_AV	= 1<<30, /* Soft Reset for Vmain_av De-Glitch */
119 	P_CTL_BYPASS_VMAIN_AV	= 1<<29, /* Bypass En. for Vmain_av De-Glitch */
120 	P_CTL_TIM_VMAIN_AV_MSK	= 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
121 					 /* Bit 26..16: Release Clock on Event */
122 	P_REL_PCIE_RST_DE_ASS	= 1<<26, /* PCIe Reset De-Asserted */
123 	P_REL_GPHY_REC_PACKET	= 1<<25, /* GPHY Received Packet */
124 	P_REL_INT_FIFO_N_EMPTY	= 1<<24, /* Internal FIFO Not Empty */
125 	P_REL_MAIN_PWR_AVAIL	= 1<<23, /* Main Power Available */
126 	P_REL_CLKRUN_REQ_REL	= 1<<22, /* CLKRUN Request Release */
127 	P_REL_PCIE_RESET_ASS	= 1<<21, /* PCIe Reset Asserted */
128 	P_REL_PME_ASSERTED	= 1<<20, /* PME Asserted */
129 	P_REL_PCIE_EXIT_L1_ST	= 1<<19, /* PCIe Exit L1 State */
130 	P_REL_LOADER_NOT_FIN	= 1<<18, /* EPROM Loader Not Finished */
131 	P_REL_PCIE_RX_EX_IDLE	= 1<<17, /* PCIe Rx Exit Electrical Idle State */
132 	P_REL_GPHY_LINK_UP	= 1<<16, /* GPHY Link Up */
133 
134 					/* Bit 10.. 0: Mask for Gate Clock */
135 	P_GAT_PCIE_RST_ASSERTED	= 1<<10,/* PCIe Reset Asserted */
136 	P_GAT_GPHY_N_REC_PACKET	= 1<<9, /* GPHY Not Received Packet */
137 	P_GAT_INT_FIFO_EMPTY	= 1<<8, /* Internal FIFO Empty */
138 	P_GAT_MAIN_PWR_N_AVAIL	= 1<<7, /* Main Power Not Available */
139 	P_GAT_CLKRUN_REQ_REL	= 1<<6, /* CLKRUN Not Requested */
140 	P_GAT_PCIE_RESET_ASS	= 1<<5, /* PCIe Reset Asserted */
141 	P_GAT_PME_DE_ASSERTED	= 1<<4, /* PME De-Asserted */
142 	P_GAT_PCIE_ENTER_L1_ST	= 1<<3, /* PCIe Enter L1 State */
143 	P_GAT_LOADER_FINISHED	= 1<<2, /* EPROM Loader Finished */
144 	P_GAT_PCIE_RX_EL_IDLE	= 1<<1, /* PCIe Rx Electrical Idle State */
145 	P_GAT_GPHY_LINK_DOWN	= 1<<0,	/* GPHY Link Down */
146 
147 	PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
148 				     P_REL_INT_FIFO_N_EMPTY |
149 				     P_REL_PCIE_EXIT_L1_ST |
150 				     P_REL_PCIE_RX_EX_IDLE |
151 				     P_GAT_GPHY_N_REC_PACKET |
152 				     P_GAT_INT_FIFO_EMPTY |
153 				     P_GAT_PCIE_ENTER_L1_ST |
154 				     P_GAT_PCIE_RX_EL_IDLE,
155 };
156 
157 /*	PCI_CFG_REG_1			32 bit	Config Register 1 (Yukon-Ext only) */
158 enum pci_cfg_reg1 {
159 	P_CF1_DIS_REL_EVT_RST	= 1<<24, /* Dis. Rel. Event during PCIE reset */
160 										/* Bit 23..21: Release Clock on Event */
161 	P_CF1_REL_LDR_NOT_FIN	= 1<<23, /* EEPROM Loader Not Finished */
162 	P_CF1_REL_VMAIN_AVLBL	= 1<<22, /* Vmain available */
163 	P_CF1_REL_PCIE_RESET	= 1<<21, /* PCI-E reset */
164 										/* Bit 20..18: Gate Clock on Event */
165 	P_CF1_GAT_LDR_NOT_FIN	= 1<<20, /* EEPROM Loader Finished */
166 	P_CF1_GAT_PCIE_RX_IDLE	= 1<<19, /* PCI-E Rx Electrical idle */
167 	P_CF1_GAT_PCIE_RESET	= 1<<18, /* PCI-E Reset */
168 	P_CF1_PRST_PHY_CLKREQ	= 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
169 	P_CF1_PCIE_RST_CLKREQ	= 1<<16, /* Enable PCI-E rst generate CLKREQ */
170 
171 	P_CF1_ENA_CFG_LDR_DONE	= 1<<8, /* Enable core level Config loader done */
172 
173 	P_CF1_ENA_TXBMU_RD_IDLE	= 1<<1, /* Enable TX BMU Read  IDLE for ASPM */
174 	P_CF1_ENA_TXBMU_WR_IDLE	= 1<<0, /* Enable TX BMU Write IDLE for ASPM */
175 
176 	PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
177 					P_CF1_REL_LDR_NOT_FIN |
178 					P_CF1_REL_VMAIN_AVLBL |
179 					P_CF1_REL_PCIE_RESET |
180 					P_CF1_GAT_LDR_NOT_FIN |
181 					P_CF1_GAT_PCIE_RESET |
182 					P_CF1_PRST_PHY_CLKREQ |
183 					P_CF1_ENA_CFG_LDR_DONE |
184 					P_CF1_ENA_TXBMU_RD_IDLE |
185 					P_CF1_ENA_TXBMU_WR_IDLE,
186 };
187 
188 /* Yukon-Optima */
189 enum {
190 	PSM_CONFIG_REG1_AC_PRESENT_STATUS = 1<<31,   /* AC Present Status */
191 
192 	PSM_CONFIG_REG1_PTP_CLK_SEL	  = 1<<29,   /* PTP Clock Select */
193 	PSM_CONFIG_REG1_PTP_MODE	  = 1<<28,   /* PTP Mode */
194 
195 	PSM_CONFIG_REG1_MUX_PHY_LINK	  = 1<<27,   /* PHY Energy Detect Event */
196 
197 	PSM_CONFIG_REG1_EN_PIN63_AC_PRESENT = 1<<26,  /* Enable LED_DUPLEX for ac_present */
198 	PSM_CONFIG_REG1_EN_PCIE_TIMER	  = 1<<25,    /* Enable PCIe Timer */
199 	PSM_CONFIG_REG1_EN_SPU_TIMER	  = 1<<24,    /* Enable SPU Timer */
200 	PSM_CONFIG_REG1_POLARITY_AC_PRESENT = 1<<23,  /* AC Present Polarity */
201 
202 	PSM_CONFIG_REG1_EN_AC_PRESENT	  = 1<<21,    /* Enable AC Present */
203 
204 	PSM_CONFIG_REG1_EN_GPHY_INT_PSM	= 1<<20,      /* Enable GPHY INT for PSM */
205 	PSM_CONFIG_REG1_DIS_PSM_TIMER	= 1<<19,      /* Disable PSM Timer */
206 };
207 
208 /* Yukon-Supreme */
209 enum {
210 	PSM_CONFIG_REG1_GPHY_ENERGY_STS	= 1<<31, /* GPHY Energy Detect Status */
211 
212 	PSM_CONFIG_REG1_UART_MODE_MSK	= 3<<29, /* UART_Mode */
213 	PSM_CONFIG_REG1_CLK_RUN_ASF	= 1<<28, /* Enable Clock Free Running for ASF Subsystem */
214 	PSM_CONFIG_REG1_UART_CLK_DISABLE= 1<<27, /* Disable UART clock */
215 	PSM_CONFIG_REG1_VAUX_ONE	= 1<<26, /* Tie internal Vaux to 1'b1 */
216 	PSM_CONFIG_REG1_UART_FC_RI_VAL	= 1<<25, /* Default value for UART_RI_n */
217 	PSM_CONFIG_REG1_UART_FC_DCD_VAL	= 1<<24, /* Default value for UART_DCD_n */
218 	PSM_CONFIG_REG1_UART_FC_DSR_VAL	= 1<<23, /* Default value for UART_DSR_n */
219 	PSM_CONFIG_REG1_UART_FC_CTS_VAL	= 1<<22, /* Default value for UART_CTS_n */
220 	PSM_CONFIG_REG1_LATCH_VAUX	= 1<<21, /* Enable Latch current Vaux_avlbl */
221 	PSM_CONFIG_REG1_FORCE_TESTMODE_INPUT= 1<<20, /* Force Testmode pin as input PAD */
222 	PSM_CONFIG_REG1_UART_RST	= 1<<19, /* UART_RST */
223 	PSM_CONFIG_REG1_PSM_PCIE_L1_POL	= 1<<18, /* PCIE L1 Event Polarity for PSM */
224 	PSM_CONFIG_REG1_TIMER_STAT	= 1<<17, /* PSM Timer Status */
225 	PSM_CONFIG_REG1_GPHY_INT	= 1<<16, /* GPHY INT Status */
226 	PSM_CONFIG_REG1_FORCE_TESTMODE_ZERO= 1<<15, /* Force internal Testmode as 1'b0 */
227 	PSM_CONFIG_REG1_EN_INT_ASPM_CLKREQ = 1<<14, /* ENABLE INT for CLKRUN on ASPM and CLKREQ */
228 	PSM_CONFIG_REG1_EN_SND_TASK_ASPM_CLKREQ	= 1<<13, /* ENABLE Snd_task for CLKRUN on ASPM and CLKREQ */
229 	PSM_CONFIG_REG1_DIS_CLK_GATE_SND_TASK	= 1<<12, /* Disable CLK_GATE control snd_task */
230 	PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA	= 1<<11, /* Disable flip-flop chain for sndmsg_inta */
231 
232 	PSM_CONFIG_REG1_DIS_LOADER	= 1<<9, /* Disable Loader SM after PSM Goes back to IDLE */
233 	PSM_CONFIG_REG1_DO_PWDN		= 1<<8, /* Do Power Down, Start PSM Scheme */
234 	PSM_CONFIG_REG1_DIS_PIG		= 1<<7, /* Disable Plug-in-Go SM after PSM Goes back to IDLE */
235 	PSM_CONFIG_REG1_DIS_PERST	= 1<<6, /* Disable Internal PCIe Reset after PSM Goes back to IDLE */
236 	PSM_CONFIG_REG1_EN_REG18_PD	= 1<<5, /* Enable REG18 Power Down for PSM */
237 	PSM_CONFIG_REG1_EN_PSM_LOAD	= 1<<4, /* Disable EEPROM Loader after PSM Goes back to IDLE */
238 	PSM_CONFIG_REG1_EN_PSM_HOT_RST	= 1<<3, /* Enable PCIe Hot Reset for PSM */
239 	PSM_CONFIG_REG1_EN_PSM_PERST	= 1<<2, /* Enable PCIe Reset Event for PSM */
240 	PSM_CONFIG_REG1_EN_PSM_PCIE_L1	= 1<<1, /* Enable PCIe L1 Event for PSM */
241 	PSM_CONFIG_REG1_EN_PSM		= 1<<0, /* Enable PSM Scheme */
242 };
243 
244 /*	PSM_CONFIG_REG4				0x0168	PSM Config Register 4 */
245 enum {
246 						/* PHY Link Detect Timer */
247 	PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK = 0xf<<4,
248 	PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE = 4,
249 
250 	PSM_CONFIG_REG4_DEBUG_TIMER	    = 1<<1, /* Debug Timer */
251 	PSM_CONFIG_REG4_RST_PHY_LINK_DETECT = 1<<0, /* Reset GPHY Link Detect */
252 };
253 
254 
255 enum csr_regs {
256 	B0_RAP		= 0x0000,
257 	B0_CTST		= 0x0004,
258 
259 	B0_POWER_CTRL	= 0x0007,
260 	B0_ISRC		= 0x0008,
261 	B0_IMSK		= 0x000c,
262 	B0_HWE_ISRC	= 0x0010,
263 	B0_HWE_IMSK	= 0x0014,
264 
265 	/* Special ISR registers (Yukon-2 only) */
266 	B0_Y2_SP_ISRC2	= 0x001c,
267 	B0_Y2_SP_ISRC3	= 0x0020,
268 	B0_Y2_SP_EISR	= 0x0024,
269 	B0_Y2_SP_LISR	= 0x0028,
270 	B0_Y2_SP_ICR	= 0x002c,
271 
272 	B2_MAC_1	= 0x0100,
273 	B2_MAC_2	= 0x0108,
274 	B2_MAC_3	= 0x0110,
275 	B2_CONN_TYP	= 0x0118,
276 	B2_PMD_TYP	= 0x0119,
277 	B2_MAC_CFG	= 0x011a,
278 	B2_CHIP_ID	= 0x011b,
279 	B2_E_0		= 0x011c,
280 
281 	B2_Y2_CLK_GATE  = 0x011d,
282 	B2_Y2_HW_RES	= 0x011e,
283 	B2_E_3		= 0x011f,
284 	B2_Y2_CLK_CTRL	= 0x0120,
285 
286 	B2_TI_INI	= 0x0130,
287 	B2_TI_VAL	= 0x0134,
288 	B2_TI_CTRL	= 0x0138,
289 	B2_TI_TEST	= 0x0139,
290 
291 	B2_TST_CTRL1	= 0x0158,
292 	B2_TST_CTRL2	= 0x0159,
293 	B2_GP_IO	= 0x015c,
294 
295 	B2_I2C_CTRL	= 0x0160,
296 	B2_I2C_DATA	= 0x0164,
297 	B2_I2C_IRQ	= 0x0168,
298 	B2_I2C_SW	= 0x016c,
299 
300 	Y2_PEX_PHY_DATA = 0x0170,
301 	Y2_PEX_PHY_ADDR = 0x0172,
302 
303 	B3_RAM_ADDR	= 0x0180,
304 	B3_RAM_DATA_LO	= 0x0184,
305 	B3_RAM_DATA_HI	= 0x0188,
306 
307 /* RAM Interface Registers */
308 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
309 /*
310  * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
311  * not usable in SW. Please notice these are NOT real timeouts, these are
312  * the number of qWords transferred continuously.
313  */
314 #define RAM_BUFFER(port, reg)	(reg | (port <<6))
315 
316 	B3_RI_WTO_R1	= 0x0190,
317 	B3_RI_WTO_XA1	= 0x0191,
318 	B3_RI_WTO_XS1	= 0x0192,
319 	B3_RI_RTO_R1	= 0x0193,
320 	B3_RI_RTO_XA1	= 0x0194,
321 	B3_RI_RTO_XS1	= 0x0195,
322 	B3_RI_WTO_R2	= 0x0196,
323 	B3_RI_WTO_XA2	= 0x0197,
324 	B3_RI_WTO_XS2	= 0x0198,
325 	B3_RI_RTO_R2	= 0x0199,
326 	B3_RI_RTO_XA2	= 0x019a,
327 	B3_RI_RTO_XS2	= 0x019b,
328 	B3_RI_TO_VAL	= 0x019c,
329 	B3_RI_CTRL	= 0x01a0,
330 	B3_RI_TEST	= 0x01a2,
331 	B3_MA_TOINI_RX1	= 0x01b0,
332 	B3_MA_TOINI_RX2	= 0x01b1,
333 	B3_MA_TOINI_TX1	= 0x01b2,
334 	B3_MA_TOINI_TX2	= 0x01b3,
335 	B3_MA_TOVAL_RX1	= 0x01b4,
336 	B3_MA_TOVAL_RX2	= 0x01b5,
337 	B3_MA_TOVAL_TX1	= 0x01b6,
338 	B3_MA_TOVAL_TX2	= 0x01b7,
339 	B3_MA_TO_CTRL	= 0x01b8,
340 	B3_MA_TO_TEST	= 0x01ba,
341 	B3_MA_RCINI_RX1	= 0x01c0,
342 	B3_MA_RCINI_RX2	= 0x01c1,
343 	B3_MA_RCINI_TX1	= 0x01c2,
344 	B3_MA_RCINI_TX2	= 0x01c3,
345 	B3_MA_RCVAL_RX1	= 0x01c4,
346 	B3_MA_RCVAL_RX2	= 0x01c5,
347 	B3_MA_RCVAL_TX1	= 0x01c6,
348 	B3_MA_RCVAL_TX2	= 0x01c7,
349 	B3_MA_RC_CTRL	= 0x01c8,
350 	B3_MA_RC_TEST	= 0x01ca,
351 	B3_PA_TOINI_RX1	= 0x01d0,
352 	B3_PA_TOINI_RX2	= 0x01d4,
353 	B3_PA_TOINI_TX1	= 0x01d8,
354 	B3_PA_TOINI_TX2	= 0x01dc,
355 	B3_PA_TOVAL_RX1	= 0x01e0,
356 	B3_PA_TOVAL_RX2	= 0x01e4,
357 	B3_PA_TOVAL_TX1	= 0x01e8,
358 	B3_PA_TOVAL_TX2	= 0x01ec,
359 	B3_PA_CTRL	= 0x01f0,
360 	B3_PA_TEST	= 0x01f2,
361 
362 	Y2_CFG_SPC	= 0x1c00,	/* PCI config space region */
363 	Y2_CFG_AER      = 0x1d00,	/* PCI Advanced Error Report region */
364 };
365 
366 /*	B0_CTST			24 bit	Control/Status register */
367 enum {
368 	Y2_VMAIN_AVAIL	= 1<<17,/* VMAIN available (YUKON-2 only) */
369 	Y2_VAUX_AVAIL	= 1<<16,/* VAUX available (YUKON-2 only) */
370 	Y2_HW_WOL_ON	= 1<<15,/* HW WOL On  (Yukon-EC Ultra A1 only) */
371 	Y2_HW_WOL_OFF	= 1<<14,/* HW WOL On  (Yukon-EC Ultra A1 only) */
372 	Y2_ASF_ENABLE	= 1<<13,/* ASF Unit Enable (YUKON-2 only) */
373 	Y2_ASF_DISABLE	= 1<<12,/* ASF Unit Disable (YUKON-2 only) */
374 	Y2_CLK_RUN_ENA	= 1<<11,/* CLK_RUN Enable  (YUKON-2 only) */
375 	Y2_CLK_RUN_DIS	= 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
376 	Y2_LED_STAT_ON	= 1<<9, /* Status LED On  (YUKON-2 only) */
377 	Y2_LED_STAT_OFF	= 1<<8, /* Status LED Off (YUKON-2 only) */
378 
379 	CS_ST_SW_IRQ	= 1<<7,	/* Set IRQ SW Request */
380 	CS_CL_SW_IRQ	= 1<<6,	/* Clear IRQ SW Request */
381 	CS_STOP_DONE	= 1<<5,	/* Stop Master is finished */
382 	CS_STOP_MAST	= 1<<4,	/* Command Bit to stop the master */
383 	CS_MRST_CLR	= 1<<3,	/* Clear Master reset	*/
384 	CS_MRST_SET	= 1<<2,	/* Set Master reset	*/
385 	CS_RST_CLR	= 1<<1,	/* Clear Software reset	*/
386 	CS_RST_SET	= 1,	/* Set   Software reset	*/
387 };
388 
389 /*	B0_POWER_CTRL	 8 Bit	Power Control reg (YUKON only) */
390 enum {
391 	PC_VAUX_ENA	= 1<<7,	/* Switch VAUX Enable  */
392 	PC_VAUX_DIS	= 1<<6,	/* Switch VAUX Disable */
393 	PC_VCC_ENA	= 1<<5,	/* Switch VCC Enable  */
394 	PC_VCC_DIS	= 1<<4,	/* Switch VCC Disable */
395 	PC_VAUX_ON	= 1<<3,	/* Switch VAUX On  */
396 	PC_VAUX_OFF	= 1<<2,	/* Switch VAUX Off */
397 	PC_VCC_ON	= 1<<1,	/* Switch VCC On  */
398 	PC_VCC_OFF	= 1<<0,	/* Switch VCC Off */
399 };
400 
401 /*	B2_IRQM_MSK 	32 bit	IRQ Moderation Mask */
402 
403 /*	B0_Y2_SP_ISRC2	32 bit	Special Interrupt Source Reg 2 */
404 /*	B0_Y2_SP_ISRC3	32 bit	Special Interrupt Source Reg 3 */
405 /*	B0_Y2_SP_EISR	32 bit	Enter ISR Reg */
406 /*	B0_Y2_SP_LISR	32 bit	Leave ISR Reg */
407 enum {
408 	Y2_IS_HW_ERR	= 1<<31,	/* Interrupt HW Error */
409 	Y2_IS_STAT_BMU	= 1<<30,	/* Status BMU Interrupt */
410 	Y2_IS_ASF	= 1<<29,	/* ASF subsystem Interrupt */
411 	Y2_IS_CPU_TO	= 1<<28,	/* CPU Timeout */
412 	Y2_IS_POLL_CHK	= 1<<27,	/* Check IRQ from polling unit */
413 	Y2_IS_TWSI_RDY	= 1<<26,	/* IRQ on end of TWSI Tx */
414 	Y2_IS_IRQ_SW	= 1<<25,	/* SW forced IRQ	*/
415 	Y2_IS_TIMINT	= 1<<24,	/* IRQ from Timer	*/
416 
417 	Y2_IS_IRQ_PHY2	= 1<<12,	/* Interrupt from PHY 2 */
418 	Y2_IS_IRQ_MAC2	= 1<<11,	/* Interrupt from MAC 2 */
419 	Y2_IS_CHK_RX2	= 1<<10,	/* Descriptor error Rx 2 */
420 	Y2_IS_CHK_TXS2	= 1<<9,		/* Descriptor error TXS 2 */
421 	Y2_IS_CHK_TXA2	= 1<<8,		/* Descriptor error TXA 2 */
422 
423 	Y2_IS_PSM_ACK	= 1<<7,		/* PSM Acknowledge (Yukon-Optima only) */
424 	Y2_IS_PTP_TIST	= 1<<6,		/* PTP Time Stamp (Yukon-Optima only) */
425 	Y2_IS_PHY_QLNK	= 1<<5,		/* PHY Quick Link (Yukon-Optima only) */
426 
427 	Y2_IS_IRQ_PHY1	= 1<<4,		/* Interrupt from PHY 1 */
428 	Y2_IS_IRQ_MAC1	= 1<<3,		/* Interrupt from MAC 1 */
429 	Y2_IS_CHK_RX1	= 1<<2,		/* Descriptor error Rx 1 */
430 	Y2_IS_CHK_TXS1	= 1<<1,		/* Descriptor error TXS 1 */
431 	Y2_IS_CHK_TXA1	= 1<<0,		/* Descriptor error TXA 1 */
432 
433 	Y2_IS_BASE	= Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
434 	Y2_IS_PORT_1	= Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
435 		          | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
436 	Y2_IS_PORT_2	= Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
437 			  | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
438 	Y2_IS_ERROR     = Y2_IS_HW_ERR |
439 			  Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 |
440 			  Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
441 };
442 
443 /*	B2_IRQM_HWE_MSK	32 bit	IRQ Moderation HW Error Mask */
444 enum {
445 	IS_ERR_MSK	= 0x00003fff,/* 		All Error bits */
446 
447 	IS_IRQ_TIST_OV	= 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
448 	IS_IRQ_SENSOR	= 1<<12, /* IRQ from Sensor (YUKON only) */
449 	IS_IRQ_MST_ERR	= 1<<11, /* IRQ master error detected */
450 	IS_IRQ_STAT	= 1<<10, /* IRQ status exception */
451 	IS_NO_STAT_M1	= 1<<9,	/* No Rx Status from MAC 1 */
452 	IS_NO_STAT_M2	= 1<<8,	/* No Rx Status from MAC 2 */
453 	IS_NO_TIST_M1	= 1<<7,	/* No Time Stamp from MAC 1 */
454 	IS_NO_TIST_M2	= 1<<6,	/* No Time Stamp from MAC 2 */
455 	IS_RAM_RD_PAR	= 1<<5,	/* RAM Read  Parity Error */
456 	IS_RAM_WR_PAR	= 1<<4,	/* RAM Write Parity Error */
457 	IS_M1_PAR_ERR	= 1<<3,	/* MAC 1 Parity Error */
458 	IS_M2_PAR_ERR	= 1<<2,	/* MAC 2 Parity Error */
459 	IS_R1_PAR_ERR	= 1<<1,	/* Queue R1 Parity Error */
460 	IS_R2_PAR_ERR	= 1<<0,	/* Queue R2 Parity Error */
461 };
462 
463 /* Hardware error interrupt mask for Yukon 2 */
464 enum {
465 	Y2_IS_TIST_OV	= 1<<29,/* Time Stamp Timer overflow interrupt */
466 	Y2_IS_SENSOR	= 1<<28, /* Sensor interrupt */
467 	Y2_IS_MST_ERR	= 1<<27, /* Master error interrupt */
468 	Y2_IS_IRQ_STAT	= 1<<26, /* Status exception interrupt */
469 	Y2_IS_PCI_EXP	= 1<<25, /* PCI-Express interrupt */
470 	Y2_IS_PCI_NEXP	= 1<<24, /* PCI-Express error similar to PCI error */
471 						/* Link 2 */
472 	Y2_IS_PAR_RD2	= 1<<13, /* Read RAM parity error interrupt */
473 	Y2_IS_PAR_WR2	= 1<<12, /* Write RAM parity error interrupt */
474 	Y2_IS_PAR_MAC2	= 1<<11, /* MAC hardware fault interrupt */
475 	Y2_IS_PAR_RX2	= 1<<10, /* Parity Error Rx Queue 2 */
476 	Y2_IS_TCP_TXS2	= 1<<9, /* TCP length mismatch sync Tx queue IRQ */
477 	Y2_IS_TCP_TXA2	= 1<<8, /* TCP length mismatch async Tx queue IRQ */
478 						/* Link 1 */
479 	Y2_IS_PAR_RD1	= 1<<5, /* Read RAM parity error interrupt */
480 	Y2_IS_PAR_WR1	= 1<<4, /* Write RAM parity error interrupt */
481 	Y2_IS_PAR_MAC1	= 1<<3, /* MAC hardware fault interrupt */
482 	Y2_IS_PAR_RX1	= 1<<2, /* Parity Error Rx Queue 1 */
483 	Y2_IS_TCP_TXS1	= 1<<1, /* TCP length mismatch sync Tx queue IRQ */
484 	Y2_IS_TCP_TXA1	= 1<<0, /* TCP length mismatch async Tx queue IRQ */
485 
486 	Y2_HWE_L1_MASK	= Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
487 			  Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
488 	Y2_HWE_L2_MASK	= Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
489 			  Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
490 
491 	Y2_HWE_ALL_MASK	= Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
492 			  Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
493 };
494 
495 /*	B28_DPT_CTRL	 8 bit	Descriptor Poll Timer Ctrl Reg */
496 enum {
497 	DPT_START	= 1<<1,
498 	DPT_STOP	= 1<<0,
499 };
500 
501 /*	B2_TST_CTRL1	 8 bit	Test Control Register 1 */
502 enum {
503 	TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
504 	TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
505 	TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
506 	TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
507 	TST_FRC_APERR_M	 = 1<<3, /* force ADDRPERR on MST */
508 	TST_FRC_APERR_T	 = 1<<2, /* force ADDRPERR on TRG */
509 	TST_CFG_WRITE_ON = 1<<1, /* Enable  Config Reg WR */
510 	TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
511 };
512 
513 /* 	B2_GPIO */
514 enum {
515 	GLB_GPIO_CLK_DEB_ENA = 1<<31,	/* Clock Debug Enable */
516 	GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
517 
518 	GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
519 	GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
520 	GLB_GPIO_STAT_RACE_DIS	= 1<<13, /* Status Race Disable */
521 	GLB_GPIO_TEST_SEL_MSK	= 3<<11, /* Testmode Select */
522 	GLB_GPIO_TEST_SEL_BASE	= 1<<11,
523 	GLB_GPIO_RAND_ENA	= 1<<10, /* Random Enable */
524 	GLB_GPIO_RAND_BIT_1	= 1<<9,  /* Random Bit 1 */
525 };
526 
527 /*	B2_MAC_CFG		 8 bit	MAC Configuration / Chip Revision */
528 enum {
529 	CFG_CHIP_R_MSK	  = 0xf<<4,	/* Bit 7.. 4: Chip Revision */
530 					/* Bit 3.. 2:	reserved */
531 	CFG_DIS_M2_CLK	  = 1<<1,	/* Disable Clock for 2nd MAC */
532 	CFG_SNG_MAC	  = 1<<0,	/* MAC Config: 0=2 MACs / 1=1 MAC*/
533 };
534 
535 /*	B2_CHIP_ID		 8 bit 	Chip Identification Number */
536 enum {
537 	CHIP_ID_YUKON_XL   = 0xb3, /* YUKON-2 XL */
538 	CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
539 	CHIP_ID_YUKON_EX   = 0xb5, /* YUKON-2 Extreme */
540 	CHIP_ID_YUKON_EC   = 0xb6, /* YUKON-2 EC */
541  	CHIP_ID_YUKON_FE   = 0xb7, /* YUKON-2 FE */
542  	CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
543 	CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
544 	CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
545 	CHIP_ID_YUKON_OPT  = 0xbc, /* YUKON-2 Optima */
546 	CHIP_ID_YUKON_PRM  = 0xbd, /* YUKON-2 Optima Prime */
547 	CHIP_ID_YUKON_OP_2 = 0xbe, /* YUKON-2 Optima 2 */
548 };
549 
550 enum yukon_xl_rev {
551 	CHIP_REV_YU_XL_A0  = 0,
552 	CHIP_REV_YU_XL_A1  = 1,
553 	CHIP_REV_YU_XL_A2  = 2,
554 	CHIP_REV_YU_XL_A3  = 3,
555 };
556 
557 enum yukon_ec_rev {
558 	CHIP_REV_YU_EC_A1    = 0,  /* Chip Rev. for Yukon-EC A1/A0 */
559 	CHIP_REV_YU_EC_A2    = 1,  /* Chip Rev. for Yukon-EC A2 */
560 	CHIP_REV_YU_EC_A3    = 2,  /* Chip Rev. for Yukon-EC A3 */
561 };
562 enum yukon_ec_u_rev {
563 	CHIP_REV_YU_EC_U_A0  = 1,
564 	CHIP_REV_YU_EC_U_A1  = 2,
565 	CHIP_REV_YU_EC_U_B0  = 3,
566 	CHIP_REV_YU_EC_U_B1  = 5,
567 };
568 enum yukon_fe_rev {
569 	CHIP_REV_YU_FE_A1    = 1,
570 	CHIP_REV_YU_FE_A2    = 2,
571 };
572 enum yukon_fe_p_rev {
573 	CHIP_REV_YU_FE2_A0   = 0,
574 };
575 enum yukon_ex_rev {
576 	CHIP_REV_YU_EX_A0    = 1,
577 	CHIP_REV_YU_EX_B0    = 2,
578 };
579 enum yukon_supr_rev {
580 	CHIP_REV_YU_SU_A0    = 0,
581 	CHIP_REV_YU_SU_B0    = 1,
582 	CHIP_REV_YU_SU_B1    = 3,
583 };
584 
585 enum yukon_prm_rev {
586 	CHIP_REV_YU_PRM_Z1   = 1,
587 	CHIP_REV_YU_PRM_A0   = 2,
588 };
589 
590 /*	B2_Y2_CLK_GATE	 8 bit	Clock Gating (Yukon-2 only) */
591 enum {
592 	Y2_STATUS_LNK2_INAC	= 1<<7, /* Status Link 2 inactive (0 = active) */
593 	Y2_CLK_GAT_LNK2_DIS	= 1<<6, /* Disable clock gating Link 2 */
594 	Y2_COR_CLK_LNK2_DIS	= 1<<5, /* Disable Core clock Link 2 */
595 	Y2_PCI_CLK_LNK2_DIS	= 1<<4, /* Disable PCI clock Link 2 */
596 	Y2_STATUS_LNK1_INAC	= 1<<3, /* Status Link 1 inactive (0 = active) */
597 	Y2_CLK_GAT_LNK1_DIS	= 1<<2, /* Disable clock gating Link 1 */
598 	Y2_COR_CLK_LNK1_DIS	= 1<<1, /* Disable Core clock Link 1 */
599 	Y2_PCI_CLK_LNK1_DIS	= 1<<0, /* Disable PCI clock Link 1 */
600 };
601 
602 /*	B2_Y2_HW_RES	8 bit	HW Resources (Yukon-2 only) */
603 enum {
604 	CFG_LED_MODE_MSK	= 7<<2,	/* Bit  4.. 2:	LED Mode Mask */
605 	CFG_LINK_2_AVAIL	= 1<<1,	/* Link 2 available */
606 	CFG_LINK_1_AVAIL	= 1<<0,	/* Link 1 available */
607 };
608 #define CFG_LED_MODE(x)		(((x) & CFG_LED_MODE_MSK) >> 2)
609 #define CFG_DUAL_MAC_MSK	(CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
610 
611 
612 /* B2_Y2_CLK_CTRL	32 bit	Clock Frequency Control Register (Yukon-2/EC) */
613 enum {
614 	Y2_CLK_DIV_VAL_MSK	= 0xff<<16,/* Bit 23..16: Clock Divisor Value */
615 #define	Y2_CLK_DIV_VAL(x)	(((x)<<16) & Y2_CLK_DIV_VAL_MSK)
616 	Y2_CLK_DIV_VAL2_MSK	= 7<<21,   /* Bit 23..21: Clock Divisor Value */
617 	Y2_CLK_SELECT2_MSK	= 0x1f<<16,/* Bit 20..16: Clock Select */
618 #define Y2_CLK_DIV_VAL_2(x)	(((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
619 #define Y2_CLK_SEL_VAL_2(x)	(((x)<<16) & Y2_CLK_SELECT2_MSK)
620 	Y2_CLK_DIV_ENA		= 1<<1, /* Enable  Core Clock Division */
621 	Y2_CLK_DIV_DIS		= 1<<0,	/* Disable Core Clock Division */
622 };
623 
624 /*	B2_TI_CTRL		 8 bit	Timer control */
625 /*	B2_IRQM_CTRL	 8 bit	IRQ Moderation Timer Control */
626 enum {
627 	TIM_START	= 1<<2,	/* Start Timer */
628 	TIM_STOP	= 1<<1,	/* Stop  Timer */
629 	TIM_CLR_IRQ	= 1<<0,	/* Clear Timer IRQ (!IRQM) */
630 };
631 
632 /*	B2_TI_TEST		 8 Bit	Timer Test */
633 /*	B2_IRQM_TEST	 8 bit	IRQ Moderation Timer Test */
634 /*	B28_DPT_TST		 8 bit	Descriptor Poll Timer Test Reg */
635 enum {
636 	TIM_T_ON	= 1<<2,	/* Test mode on */
637 	TIM_T_OFF	= 1<<1,	/* Test mode off */
638 	TIM_T_STEP	= 1<<0,	/* Test step */
639 };
640 
641 /*	Y2_PEX_PHY_ADDR/DATA		PEX PHY address and data reg  (Yukon-2 only) */
642 enum {
643 	PEX_RD_ACCESS	= 1<<31, /* Access Mode Read = 1, Write = 0 */
644 	PEX_DB_ACCESS	= 1<<30, /* Access to debug register */
645 };
646 
647 /*	B3_RAM_ADDR		32 bit	RAM Address, to read or write */
648 					/* Bit 31..19:	reserved */
649 #define RAM_ADR_RAN	0x0007ffffL	/* Bit 18.. 0:	RAM Address Range */
650 /* RAM Interface Registers */
651 
652 /*	B3_RI_CTRL		16 bit	RAM Interface Control Register */
653 enum {
654 	RI_CLR_RD_PERR	= 1<<9,	/* Clear IRQ RAM Read Parity Err */
655 	RI_CLR_WR_PERR	= 1<<8,	/* Clear IRQ RAM Write Parity Err*/
656 
657 	RI_RST_CLR	= 1<<1,	/* Clear RAM Interface Reset */
658 	RI_RST_SET	= 1<<0,	/* Set   RAM Interface Reset */
659 };
660 
661 #define SK_RI_TO_53	36		/* RAM interface timeout */
662 
663 
664 /* Port related registers FIFO, and Arbiter */
665 #define SK_REG(port,reg)	(((port)<<7)+(reg))
666 
667 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
668 /*	TXA_ITI_INI		32 bit	Tx Arb Interval Timer Init Val */
669 /*	TXA_ITI_VAL		32 bit	Tx Arb Interval Timer Value */
670 /*	TXA_LIM_INI		32 bit	Tx Arb Limit Counter Init Val */
671 /*	TXA_LIM_VAL		32 bit	Tx Arb Limit Counter Value */
672 
673 #define TXA_MAX_VAL	0x00ffffffUL	/* Bit 23.. 0:	Max TXA Timer/Cnt Val */
674 
675 /*	TXA_CTRL		 8 bit	Tx Arbiter Control Register */
676 enum {
677 	TXA_ENA_FSYNC	= 1<<7,	/* Enable  force of sync Tx queue */
678 	TXA_DIS_FSYNC	= 1<<6,	/* Disable force of sync Tx queue */
679 	TXA_ENA_ALLOC	= 1<<5,	/* Enable  alloc of free bandwidth */
680 	TXA_DIS_ALLOC	= 1<<4,	/* Disable alloc of free bandwidth */
681 	TXA_START_RC	= 1<<3,	/* Start sync Rate Control */
682 	TXA_STOP_RC	= 1<<2,	/* Stop  sync Rate Control */
683 	TXA_ENA_ARB	= 1<<1,	/* Enable  Tx Arbiter */
684 	TXA_DIS_ARB	= 1<<0,	/* Disable Tx Arbiter */
685 };
686 
687 /*
688  *	Bank 4 - 5
689  */
690 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
691 enum {
692 	TXA_ITI_INI	= 0x0200,/* 32 bit	Tx Arb Interval Timer Init Val*/
693 	TXA_ITI_VAL	= 0x0204,/* 32 bit	Tx Arb Interval Timer Value */
694 	TXA_LIM_INI	= 0x0208,/* 32 bit	Tx Arb Limit Counter Init Val */
695 	TXA_LIM_VAL	= 0x020c,/* 32 bit	Tx Arb Limit Counter Value */
696 	TXA_CTRL	= 0x0210,/*  8 bit	Tx Arbiter Control Register */
697 	TXA_TEST	= 0x0211,/*  8 bit	Tx Arbiter Test Register */
698 	TXA_STAT	= 0x0212,/*  8 bit	Tx Arbiter Status Register */
699 
700 	RSS_KEY		= 0x0220, /* RSS Key setup */
701 	RSS_CFG		= 0x0248, /* RSS Configuration */
702 };
703 
704 enum {
705 	HASH_TCP_IPV6_EX_CTRL	= 1<<5,
706 	HASH_IPV6_EX_CTRL	= 1<<4,
707 	HASH_TCP_IPV6_CTRL	= 1<<3,
708 	HASH_IPV6_CTRL		= 1<<2,
709 	HASH_TCP_IPV4_CTRL	= 1<<1,
710 	HASH_IPV4_CTRL		= 1<<0,
711 
712 	HASH_ALL		= 0x3f,
713 };
714 
715 enum {
716 	B6_EXT_REG	= 0x0300,/* External registers (GENESIS only) */
717 	B7_CFG_SPC	= 0x0380,/* copy of the Configuration register */
718 	B8_RQ1_REGS	= 0x0400,/* Receive Queue 1 */
719 	B8_RQ2_REGS	= 0x0480,/* Receive Queue 2 */
720 	B8_TS1_REGS	= 0x0600,/* Transmit sync queue 1 */
721 	B8_TA1_REGS	= 0x0680,/* Transmit async queue 1 */
722 	B8_TS2_REGS	= 0x0700,/* Transmit sync queue 2 */
723 	B8_TA2_REGS	= 0x0780,/* Transmit sync queue 2 */
724 	B16_RAM_REGS	= 0x0800,/* RAM Buffer Registers */
725 };
726 
727 /* Queue Register Offsets, use Q_ADDR() to access */
728 enum {
729 	B8_Q_REGS = 0x0400, /* base of Queue registers */
730 	Q_D	= 0x00,	/* 8*32	bit	Current Descriptor */
731 	Q_VLAN  = 0x20, /* 16 bit	Current VLAN Tag */
732 	Q_DONE	= 0x24,	/* 16 bit	Done Index */
733 	Q_AC_L	= 0x28,	/* 32 bit	Current Address Counter Low dWord */
734 	Q_AC_H	= 0x2c,	/* 32 bit	Current Address Counter High dWord */
735 	Q_BC	= 0x30,	/* 32 bit	Current Byte Counter */
736 	Q_CSR	= 0x34,	/* 32 bit	BMU Control/Status Register */
737 	Q_TEST	= 0x38,	/* 32 bit	Test/Control Register */
738 
739 /* Yukon-2 */
740 	Q_WM	= 0x40,	/* 16 bit	FIFO Watermark */
741 	Q_AL	= 0x42,	/*  8 bit	FIFO Alignment */
742 	Q_RSP	= 0x44,	/* 16 bit	FIFO Read Shadow Pointer */
743 	Q_RSL	= 0x46,	/*  8 bit	FIFO Read Shadow Level */
744 	Q_RP	= 0x48,	/*  8 bit	FIFO Read Pointer */
745 	Q_RL	= 0x4a,	/*  8 bit	FIFO Read Level */
746 	Q_WP	= 0x4c,	/*  8 bit	FIFO Write Pointer */
747 	Q_WSP	= 0x4d,	/*  8 bit	FIFO Write Shadow Pointer */
748 	Q_WL	= 0x4e,	/*  8 bit	FIFO Write Level */
749 	Q_WSL	= 0x4f,	/*  8 bit	FIFO Write Shadow Level */
750 };
751 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
752 
753 /*	Q_TEST				32 bit	Test Register */
754 enum {
755 	/* Transmit */
756 	F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
757 	F_TX_CHK_AUTO_ON  = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
758 
759 	/* Receive */
760 	F_M_RX_RAM_DIS	= 1<<24, /* MAC Rx RAM Read Port disable */
761 
762 	/* Hardware testbits not used */
763 };
764 
765 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
766 enum {
767 	Y2_B8_PREF_REGS		= 0x0450,
768 
769 	PREF_UNIT_CTRL		= 0x00,	/* 32 bit	Control register */
770 	PREF_UNIT_LAST_IDX	= 0x04,	/* 16 bit	Last Index */
771 	PREF_UNIT_ADDR_LO	= 0x08,	/* 32 bit	List start addr, low part */
772 	PREF_UNIT_ADDR_HI	= 0x0c,	/* 32 bit	List start addr, high part*/
773 	PREF_UNIT_GET_IDX	= 0x10,	/* 16 bit	Get Index */
774 	PREF_UNIT_PUT_IDX	= 0x14,	/* 16 bit	Put Index */
775 	PREF_UNIT_FIFO_WP	= 0x20,	/*  8 bit	FIFO write pointer */
776 	PREF_UNIT_FIFO_RP	= 0x24,	/*  8 bit	FIFO read pointer */
777 	PREF_UNIT_FIFO_WM	= 0x28,	/*  8 bit	FIFO watermark */
778 	PREF_UNIT_FIFO_LEV	= 0x2c,	/*  8 bit	FIFO level */
779 
780 	PREF_UNIT_MASK_IDX	= 0x0fff,
781 };
782 #define Y2_QADDR(q,reg)		(Y2_B8_PREF_REGS + (q) + (reg))
783 
784 /* RAM Buffer Register Offsets */
785 enum {
786 
787 	RB_START	= 0x00,/* 32 bit	RAM Buffer Start Address */
788 	RB_END	= 0x04,/* 32 bit	RAM Buffer End Address */
789 	RB_WP	= 0x08,/* 32 bit	RAM Buffer Write Pointer */
790 	RB_RP	= 0x0c,/* 32 bit	RAM Buffer Read Pointer */
791 	RB_RX_UTPP	= 0x10,/* 32 bit	Rx Upper Threshold, Pause Packet */
792 	RB_RX_LTPP	= 0x14,/* 32 bit	Rx Lower Threshold, Pause Packet */
793 	RB_RX_UTHP	= 0x18,/* 32 bit	Rx Upper Threshold, High Prio */
794 	RB_RX_LTHP	= 0x1c,/* 32 bit	Rx Lower Threshold, High Prio */
795 	/* 0x10 - 0x1f:	reserved at Tx RAM Buffer Registers */
796 	RB_PC	= 0x20,/* 32 bit	RAM Buffer Packet Counter */
797 	RB_LEV	= 0x24,/* 32 bit	RAM Buffer Level Register */
798 	RB_CTRL	= 0x28,/* 32 bit	RAM Buffer Control Register */
799 	RB_TST1	= 0x29,/*  8 bit	RAM Buffer Test Register 1 */
800 	RB_TST2	= 0x2a,/*  8 bit	RAM Buffer Test Register 2 */
801 };
802 
803 /* Receive and Transmit Queues */
804 enum {
805 	Q_R1	= 0x0000,	/* Receive Queue 1 */
806 	Q_R2	= 0x0080,	/* Receive Queue 2 */
807 	Q_XS1	= 0x0200,	/* Synchronous Transmit Queue 1 */
808 	Q_XA1	= 0x0280,	/* Asynchronous Transmit Queue 1 */
809 	Q_XS2	= 0x0300,	/* Synchronous Transmit Queue 2 */
810 	Q_XA2	= 0x0380,	/* Asynchronous Transmit Queue 2 */
811 };
812 
813 /* Different PHY Types */
814 enum {
815 	PHY_ADDR_MARV	= 0,
816 };
817 
818 #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
819 
820 
821 enum {
822 	LNK_SYNC_INI	= 0x0c30,/* 32 bit	Link Sync Cnt Init Value */
823 	LNK_SYNC_VAL	= 0x0c34,/* 32 bit	Link Sync Cnt Current Value */
824 	LNK_SYNC_CTRL	= 0x0c38,/*  8 bit	Link Sync Cnt Control Register */
825 	LNK_SYNC_TST	= 0x0c39,/*  8 bit	Link Sync Cnt Test Register */
826 
827 	LNK_LED_REG	= 0x0c3c,/*  8 bit	Link LED Register */
828 
829 /* Receive GMAC FIFO (YUKON and Yukon-2) */
830 
831 	RX_GMF_EA	= 0x0c40,/* 32 bit	Rx GMAC FIFO End Address */
832 	RX_GMF_AF_THR	= 0x0c44,/* 32 bit	Rx GMAC FIFO Almost Full Thresh. */
833 	RX_GMF_CTRL_T	= 0x0c48,/* 32 bit	Rx GMAC FIFO Control/Test */
834 	RX_GMF_FL_MSK	= 0x0c4c,/* 32 bit	Rx GMAC FIFO Flush Mask */
835 	RX_GMF_FL_THR	= 0x0c50,/* 16 bit	Rx GMAC FIFO Flush Threshold */
836 	RX_GMF_FL_CTRL	= 0x0c52,/* 16 bit	Rx GMAC FIFO Flush Control */
837 	RX_GMF_TR_THR	= 0x0c54,/* 32 bit	Rx Truncation Threshold (Yukon-2) */
838 	RX_GMF_UP_THR	= 0x0c58,/* 16 bit	Rx Upper Pause Thr (Yukon-EC_U) */
839 	RX_GMF_LP_THR	= 0x0c5a,/* 16 bit	Rx Lower Pause Thr (Yukon-EC_U) */
840 	RX_GMF_VLAN	= 0x0c5c,/* 32 bit	Rx VLAN Type Register (Yukon-2) */
841 	RX_GMF_WP	= 0x0c60,/* 32 bit	Rx GMAC FIFO Write Pointer */
842 
843 	RX_GMF_WLEV	= 0x0c68,/* 32 bit	Rx GMAC FIFO Write Level */
844 
845 	RX_GMF_RP	= 0x0c70,/* 32 bit	Rx GMAC FIFO Read Pointer */
846 
847 	RX_GMF_RLEV	= 0x0c78,/* 32 bit	Rx GMAC FIFO Read Level */
848 };
849 
850 
851 /*	Q_BC			32 bit	Current Byte Counter */
852 
853 /* BMU Control Status Registers */
854 /*	B0_R1_CSR		32 bit	BMU Ctrl/Stat Rx Queue 1 */
855 /*	B0_R2_CSR		32 bit	BMU Ctrl/Stat Rx Queue 2 */
856 /*	B0_XA1_CSR		32 bit	BMU Ctrl/Stat Sync Tx Queue 1 */
857 /*	B0_XS1_CSR		32 bit	BMU Ctrl/Stat Async Tx Queue 1 */
858 /*	B0_XA2_CSR		32 bit	BMU Ctrl/Stat Sync Tx Queue 2 */
859 /*	B0_XS2_CSR		32 bit	BMU Ctrl/Stat Async Tx Queue 2 */
860 /*	Q_CSR			32 bit	BMU Control/Status Register */
861 
862 /* Rx BMU Control / Status Registers (Yukon-2) */
863 enum {
864 	BMU_IDLE	= 1<<31, /* BMU Idle State */
865 	BMU_RX_TCP_PKT	= 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
866 	BMU_RX_IP_PKT	= 1<<29, /* Rx IP  Packet (when RSS Hash enabled) */
867 
868 	BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable  Rx RSS Hash */
869 	BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
870 	BMU_ENA_RX_CHKSUM = 1<<13, /* Enable  Rx TCP/IP Checksum Check */
871 	BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
872 	BMU_CLR_IRQ_PAR	= 1<<11, /* Clear IRQ on Parity errors (Rx) */
873 	BMU_CLR_IRQ_TCP	= 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
874 	BMU_CLR_IRQ_CHK	= 1<<10, /* Clear IRQ Check */
875 	BMU_STOP	= 1<<9, /* Stop  Rx/Tx Queue */
876 	BMU_START	= 1<<8, /* Start Rx/Tx Queue */
877 	BMU_FIFO_OP_ON	= 1<<7, /* FIFO Operational On */
878 	BMU_FIFO_OP_OFF	= 1<<6, /* FIFO Operational Off */
879 	BMU_FIFO_ENA	= 1<<5, /* Enable FIFO */
880 	BMU_FIFO_RST	= 1<<4, /* Reset  FIFO */
881 	BMU_OP_ON	= 1<<3, /* BMU Operational On */
882 	BMU_OP_OFF	= 1<<2, /* BMU Operational Off */
883 	BMU_RST_CLR	= 1<<1, /* Clear BMU Reset (Enable) */
884 	BMU_RST_SET	= 1<<0, /* Set   BMU Reset */
885 
886 	BMU_CLR_RESET	= BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
887 	BMU_OPER_INIT	= BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
888 			  BMU_FIFO_ENA | BMU_OP_ON,
889 
890 	BMU_WM_DEFAULT = 0x600,
891 	BMU_WM_PEX     = 0x80,
892 };
893 
894 /* Tx BMU Control / Status Registers (Yukon-2) */
895 								/* Bit 31: same as for Rx */
896 enum {
897 	BMU_TX_IPIDINCR_ON	= 1<<13, /* Enable  IP ID Increment */
898 	BMU_TX_IPIDINCR_OFF	= 1<<12, /* Disable IP ID Increment */
899 	BMU_TX_CLR_IRQ_TCP	= 1<<11, /* Clear IRQ on TCP segment length mismatch */
900 };
901 
902 /*	TBMU_TEST			0x06B8	Transmit BMU Test Register */
903 enum {
904 	TBMU_TEST_BMU_TX_CHK_AUTO_OFF		= 1<<31, /* BMU Tx Checksum Auto Calculation Disable */
905 	TBMU_TEST_BMU_TX_CHK_AUTO_ON		= 1<<30, /* BMU Tx Checksum Auto Calculation Enable */
906 	TBMU_TEST_HOME_ADD_PAD_FIX1_EN		= 1<<29, /* Home Address Paddiing FIX1 Enable */
907 	TBMU_TEST_HOME_ADD_PAD_FIX1_DIS		= 1<<28, /* Home Address Paddiing FIX1 Disable */
908 	TBMU_TEST_ROUTING_ADD_FIX_EN		= 1<<27, /* Routing Address Fix Enable */
909 	TBMU_TEST_ROUTING_ADD_FIX_DIS		= 1<<26, /* Routing Address Fix Disable */
910 	TBMU_TEST_HOME_ADD_FIX_EN		= 1<<25, /* Home address checksum fix enable */
911 	TBMU_TEST_HOME_ADD_FIX_DIS		= 1<<24, /* Home address checksum fix disable */
912 
913 	TBMU_TEST_TEST_RSPTR_ON			= 1<<22, /* Testmode Shadow Read Ptr On */
914 	TBMU_TEST_TEST_RSPTR_OFF		= 1<<21, /* Testmode Shadow Read Ptr Off */
915 	TBMU_TEST_TESTSTEP_RSPTR		= 1<<20, /* Teststep Shadow Read Ptr */
916 
917 	TBMU_TEST_TEST_RPTR_ON			= 1<<18, /* Testmode Read Ptr On */
918 	TBMU_TEST_TEST_RPTR_OFF			= 1<<17, /* Testmode Read Ptr Off */
919 	TBMU_TEST_TESTSTEP_RPTR			= 1<<16, /* Teststep Read Ptr */
920 
921 	TBMU_TEST_TEST_WSPTR_ON			= 1<<14, /* Testmode Shadow Write Ptr On */
922 	TBMU_TEST_TEST_WSPTR_OFF		= 1<<13, /* Testmode Shadow Write Ptr Off */
923 	TBMU_TEST_TESTSTEP_WSPTR		= 1<<12, /* Teststep Shadow Write Ptr */
924 
925 	TBMU_TEST_TEST_WPTR_ON			= 1<<10, /* Testmode Write Ptr On */
926 	TBMU_TEST_TEST_WPTR_OFF			= 1<<9, /* Testmode Write Ptr Off */
927 	TBMU_TEST_TESTSTEP_WPTR			= 1<<8,			/* Teststep Write Ptr */
928 
929 	TBMU_TEST_TEST_REQ_NB_ON		= 1<<6, /* Testmode Req Nbytes/Addr On */
930 	TBMU_TEST_TEST_REQ_NB_OFF		= 1<<5, /* Testmode Req Nbytes/Addr Off */
931 	TBMU_TEST_TESTSTEP_REQ_NB		= 1<<4, /* Teststep Req Nbytes/Addr */
932 
933 	TBMU_TEST_TEST_DONE_IDX_ON		= 1<<2, /* Testmode Done Index On */
934 	TBMU_TEST_TEST_DONE_IDX_OFF		= 1<<1, /* Testmode Done Index Off */
935 	TBMU_TEST_TESTSTEP_DONE_IDX		= 1<<0,	/* Teststep Done Index */
936 };
937 
938 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
939 /* PREF_UNIT_CTRL	32 bit	Prefetch Control register */
940 enum {
941 	PREF_UNIT_OP_ON		= 1<<3,	/* prefetch unit operational */
942 	PREF_UNIT_OP_OFF	= 1<<2,	/* prefetch unit not operational */
943 	PREF_UNIT_RST_CLR	= 1<<1,	/* Clear Prefetch Unit Reset */
944 	PREF_UNIT_RST_SET	= 1<<0,	/* Set   Prefetch Unit Reset */
945 };
946 
947 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
948 /*	RB_START		32 bit	RAM Buffer Start Address */
949 /*	RB_END			32 bit	RAM Buffer End Address */
950 /*	RB_WP			32 bit	RAM Buffer Write Pointer */
951 /*	RB_RP			32 bit	RAM Buffer Read Pointer */
952 /*	RB_RX_UTPP		32 bit	Rx Upper Threshold, Pause Pack */
953 /*	RB_RX_LTPP		32 bit	Rx Lower Threshold, Pause Pack */
954 /*	RB_RX_UTHP		32 bit	Rx Upper Threshold, High Prio */
955 /*	RB_RX_LTHP		32 bit	Rx Lower Threshold, High Prio */
956 /*	RB_PC			32 bit	RAM Buffer Packet Counter */
957 /*	RB_LEV			32 bit	RAM Buffer Level Register */
958 
959 #define RB_MSK	0x0007ffff	/* Bit 18.. 0:	RAM Buffer Pointer Bits */
960 /*	RB_TST2			 8 bit	RAM Buffer Test Register 2 */
961 /*	RB_TST1			 8 bit	RAM Buffer Test Register 1 */
962 
963 /*	RB_CTRL			 8 bit	RAM Buffer Control Register */
964 enum {
965 	RB_ENA_STFWD	= 1<<5,	/* Enable  Store & Forward */
966 	RB_DIS_STFWD	= 1<<4,	/* Disable Store & Forward */
967 	RB_ENA_OP_MD	= 1<<3,	/* Enable  Operation Mode */
968 	RB_DIS_OP_MD	= 1<<2,	/* Disable Operation Mode */
969 	RB_RST_CLR	= 1<<1,	/* Clear RAM Buf STM Reset */
970 	RB_RST_SET	= 1<<0,	/* Set   RAM Buf STM Reset */
971 };
972 
973 
974 /* Transmit GMAC FIFO (YUKON only) */
975 enum {
976 	TX_GMF_EA	= 0x0d40,/* 32 bit	Tx GMAC FIFO End Address */
977 	TX_GMF_AE_THR	= 0x0d44,/* 32 bit	Tx GMAC FIFO Almost Empty Thresh.*/
978 	TX_GMF_CTRL_T	= 0x0d48,/* 32 bit	Tx GMAC FIFO Control/Test */
979 
980 	TX_GMF_WP	= 0x0d60,/* 32 bit 	Tx GMAC FIFO Write Pointer */
981 	TX_GMF_WSP	= 0x0d64,/* 32 bit 	Tx GMAC FIFO Write Shadow Ptr. */
982 	TX_GMF_WLEV	= 0x0d68,/* 32 bit 	Tx GMAC FIFO Write Level */
983 
984 	TX_GMF_RP	= 0x0d70,/* 32 bit 	Tx GMAC FIFO Read Pointer */
985 	TX_GMF_RSTP	= 0x0d74,/* 32 bit 	Tx GMAC FIFO Restart Pointer */
986 	TX_GMF_RLEV	= 0x0d78,/* 32 bit 	Tx GMAC FIFO Read Level */
987 
988 	/* Threshold values for Yukon-EC Ultra and Extreme */
989 	ECU_AE_THR	= 0x0070, /* Almost Empty Threshold */
990 	ECU_TXFF_LEV	= 0x01a0, /* Tx BMU FIFO Level */
991 	ECU_JUMBO_WM	= 0x0080, /* Jumbo Mode Watermark */
992 };
993 
994 /* Descriptor Poll Timer Registers */
995 enum {
996 	B28_DPT_INI	= 0x0e00,/* 24 bit	Descriptor Poll Timer Init Val */
997 	B28_DPT_VAL	= 0x0e04,/* 24 bit	Descriptor Poll Timer Curr Val */
998 	B28_DPT_CTRL	= 0x0e08,/*  8 bit	Descriptor Poll Timer Ctrl Reg */
999 
1000 	B28_DPT_TST	= 0x0e0a,/*  8 bit	Descriptor Poll Timer Test Reg */
1001 };
1002 
1003 /* Time Stamp Timer Registers (YUKON only) */
1004 enum {
1005 	GMAC_TI_ST_VAL	= 0x0e14,/* 32 bit	Time Stamp Timer Curr Val */
1006 	GMAC_TI_ST_CTRL	= 0x0e18,/*  8 bit	Time Stamp Timer Ctrl Reg */
1007 	GMAC_TI_ST_TST	= 0x0e1a,/*  8 bit	Time Stamp Timer Test Reg */
1008 };
1009 
1010 /* Polling Unit Registers (Yukon-2 only) */
1011 enum {
1012 	POLL_CTRL	= 0x0e20, /* 32 bit	Polling Unit Control Reg */
1013 	POLL_LAST_IDX	= 0x0e24,/* 16 bit	Polling Unit List Last Index */
1014 
1015 	POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit	Poll. List Start Addr (low) */
1016 	POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit	Poll. List Start Addr (high) */
1017 };
1018 
1019 enum {
1020 	SMB_CFG		 = 0x0e40, /* 32 bit	SMBus Config Register */
1021 	SMB_CSR		 = 0x0e44, /* 32 bit	SMBus Control/Status Register */
1022 };
1023 
1024 enum {
1025 	CPU_WDOG	 = 0x0e48, /* 32 bit	Watchdog Register  */
1026 	CPU_CNTR	 = 0x0e4C, /* 32 bit	Counter Register  */
1027 	CPU_TIM		 = 0x0e50,/* 32 bit	Timer Compare Register  */
1028 	CPU_AHB_ADDR	 = 0x0e54, /* 32 bit	CPU AHB Debug  Register  */
1029 	CPU_AHB_WDATA	 = 0x0e58, /* 32 bit	CPU AHB Debug  Register  */
1030 	CPU_AHB_RDATA	 = 0x0e5C, /* 32 bit	CPU AHB Debug  Register  */
1031 	HCU_MAP_BASE	 = 0x0e60, /* 32 bit	Reset Mapping Base */
1032 	CPU_AHB_CTRL	 = 0x0e64, /* 32 bit	CPU AHB Debug  Register  */
1033 	HCU_CCSR	 = 0x0e68, /* 32 bit	CPU Control and Status Register */
1034 	HCU_HCSR	 = 0x0e6C, /* 32 bit	Host Control and Status Register */
1035 };
1036 
1037 /* ASF Subsystem Registers (Yukon-2 only) */
1038 enum {
1039 	B28_Y2_SMB_CONFIG  = 0x0e40,/* 32 bit	ASF SMBus Config Register */
1040 	B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit	ASF SMB Control/Status/Data */
1041 	B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit	ASF IRQ Vector Base */
1042 
1043 	B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit	ASF Status and Command Reg */
1044 	B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit	ASF Host Communication Reg */
1045 	B28_Y2_DATA_REG_1  = 0x0e70,/* 32 bit	ASF/Host Data Register 1 */
1046 	B28_Y2_DATA_REG_2  = 0x0e74,/* 32 bit	ASF/Host Data Register 2 */
1047 	B28_Y2_DATA_REG_3  = 0x0e78,/* 32 bit	ASF/Host Data Register 3 */
1048 	B28_Y2_DATA_REG_4  = 0x0e7c,/* 32 bit	ASF/Host Data Register 4 */
1049 };
1050 
1051 /* Status BMU Registers (Yukon-2 only)*/
1052 enum {
1053 	STAT_CTRL	= 0x0e80,/* 32 bit	Status BMU Control Reg */
1054 	STAT_LAST_IDX	= 0x0e84,/* 16 bit	Status BMU Last Index */
1055 
1056 	STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit	Status List Start Addr (low) */
1057 	STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit	Status List Start Addr (high) */
1058 	STAT_TXA1_RIDX	= 0x0e90,/* 16 bit	Status TxA1 Report Index Reg */
1059 	STAT_TXS1_RIDX	= 0x0e92,/* 16 bit	Status TxS1 Report Index Reg */
1060 	STAT_TXA2_RIDX	= 0x0e94,/* 16 bit	Status TxA2 Report Index Reg */
1061 	STAT_TXS2_RIDX	= 0x0e96,/* 16 bit	Status TxS2 Report Index Reg */
1062 	STAT_TX_IDX_TH	= 0x0e98,/* 16 bit	Status Tx Index Threshold Reg */
1063 	STAT_PUT_IDX	= 0x0e9c,/* 16 bit	Status Put Index Reg */
1064 
1065 /* FIFO Control/Status Registers (Yukon-2 only)*/
1066 	STAT_FIFO_WP	= 0x0ea0,/*  8 bit	Status FIFO Write Pointer Reg */
1067 	STAT_FIFO_RP	= 0x0ea4,/*  8 bit	Status FIFO Read Pointer Reg */
1068 	STAT_FIFO_RSP	= 0x0ea6,/*  8 bit	Status FIFO Read Shadow Ptr */
1069 	STAT_FIFO_LEVEL	= 0x0ea8,/*  8 bit	Status FIFO Level Reg */
1070 	STAT_FIFO_SHLVL	= 0x0eaa,/*  8 bit	Status FIFO Shadow Level Reg */
1071 	STAT_FIFO_WM	= 0x0eac,/*  8 bit	Status FIFO Watermark Reg */
1072 	STAT_FIFO_ISR_WM= 0x0ead,/*  8 bit	Status FIFO ISR Watermark Reg */
1073 
1074 /* Level and ISR Timer Registers (Yukon-2 only)*/
1075 	STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit	Level Timer Init. Value Reg */
1076 	STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit	Level Timer Counter Reg */
1077 	STAT_LEV_TIMER_CTRL= 0x0eb8,/*  8 bit	Level Timer Control Reg */
1078 	STAT_LEV_TIMER_TEST= 0x0eb9,/*  8 bit	Level Timer Test Reg */
1079 	STAT_TX_TIMER_INI  = 0x0ec0,/* 32 bit	Tx Timer Init. Value Reg */
1080 	STAT_TX_TIMER_CNT  = 0x0ec4,/* 32 bit	Tx Timer Counter Reg */
1081 	STAT_TX_TIMER_CTRL = 0x0ec8,/*  8 bit	Tx Timer Control Reg */
1082 	STAT_TX_TIMER_TEST = 0x0ec9,/*  8 bit	Tx Timer Test Reg */
1083 	STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit	ISR Timer Init. Value Reg */
1084 	STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit	ISR Timer Counter Reg */
1085 	STAT_ISR_TIMER_CTRL= 0x0ed8,/*  8 bit	ISR Timer Control Reg */
1086 	STAT_ISR_TIMER_TEST= 0x0ed9,/*  8 bit	ISR Timer Test Reg */
1087 };
1088 
1089 enum {
1090 	LINKLED_OFF 	     = 0x01,
1091 	LINKLED_ON  	     = 0x02,
1092 	LINKLED_LINKSYNC_OFF = 0x04,
1093 	LINKLED_LINKSYNC_ON  = 0x08,
1094 	LINKLED_BLINK_OFF    = 0x10,
1095 	LINKLED_BLINK_ON     = 0x20,
1096 };
1097 
1098 /* GMAC and GPHY Control Registers (YUKON only) */
1099 enum {
1100 	GMAC_CTRL	= 0x0f00,/* 32 bit	GMAC Control Reg */
1101 	GPHY_CTRL	= 0x0f04,/* 32 bit	GPHY Control Reg */
1102 	GMAC_IRQ_SRC	= 0x0f08,/*  8 bit	GMAC Interrupt Source Reg */
1103 	GMAC_IRQ_MSK	= 0x0f0c,/*  8 bit	GMAC Interrupt Mask Reg */
1104 	GMAC_LINK_CTRL	= 0x0f10,/* 16 bit	Link Control Reg */
1105 
1106 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
1107 	WOL_CTRL_STAT	= 0x0f20,/* 16 bit	WOL Control/Status Reg */
1108 	WOL_MATCH_CTL	= 0x0f22,/*  8 bit	WOL Match Control Reg */
1109 	WOL_MATCH_RES	= 0x0f23,/*  8 bit	WOL Match Result Reg */
1110 	WOL_MAC_ADDR	= 0x0f24,/* 32 bit	WOL MAC Address */
1111 	WOL_PATT_RPTR	= 0x0f2c,/*  8 bit	WOL Pattern Read Pointer */
1112 
1113 /* WOL Pattern Length Registers (YUKON only) */
1114 	WOL_PATT_LEN_LO	= 0x0f30,/* 32 bit	WOL Pattern Length 3..0 */
1115 	WOL_PATT_LEN_HI	= 0x0f34,/* 24 bit	WOL Pattern Length 6..4 */
1116 
1117 /* WOL Pattern Counter Registers (YUKON only) */
1118 	WOL_PATT_CNT_0	= 0x0f38,/* 32 bit	WOL Pattern Counter 3..0 */
1119 	WOL_PATT_CNT_4	= 0x0f3c,/* 24 bit	WOL Pattern Counter 6..4 */
1120 };
1121 #define WOL_REGS(port, x)	(x + (port)*0x80)
1122 
1123 enum {
1124 	WOL_PATT_RAM_1	= 0x1000,/*  WOL Pattern RAM Link 1 */
1125 	WOL_PATT_RAM_2	= 0x1400,/*  WOL Pattern RAM Link 2 */
1126 };
1127 #define WOL_PATT_RAM_BASE(port)	(WOL_PATT_RAM_1 + (port)*0x400)
1128 
1129 enum {
1130 	BASE_GMAC_1	= 0x2800,/* GMAC 1 registers */
1131 	BASE_GMAC_2	= 0x3800,/* GMAC 2 registers */
1132 };
1133 
1134 /*
1135  * Marvel-PHY Registers, indirect addressed over GMAC
1136  */
1137 enum {
1138 	PHY_MARV_CTRL		= 0x00,/* 16 bit r/w	PHY Control Register */
1139 	PHY_MARV_STAT		= 0x01,/* 16 bit r/o	PHY Status Register */
1140 	PHY_MARV_ID0		= 0x02,/* 16 bit r/o	PHY ID0 Register */
1141 	PHY_MARV_ID1		= 0x03,/* 16 bit r/o	PHY ID1 Register */
1142 	PHY_MARV_AUNE_ADV	= 0x04,/* 16 bit r/w	Auto-Neg. Advertisement */
1143 	PHY_MARV_AUNE_LP	= 0x05,/* 16 bit r/o	Link Part Ability Reg */
1144 	PHY_MARV_AUNE_EXP	= 0x06,/* 16 bit r/o	Auto-Neg. Expansion Reg */
1145 	PHY_MARV_NEPG		= 0x07,/* 16 bit r/w	Next Page Register */
1146 	PHY_MARV_NEPG_LP	= 0x08,/* 16 bit r/o	Next Page Link Partner */
1147 	/* Marvel-specific registers */
1148 	PHY_MARV_1000T_CTRL	= 0x09,/* 16 bit r/w	1000Base-T Control Reg */
1149 	PHY_MARV_1000T_STAT	= 0x0a,/* 16 bit r/o	1000Base-T Status Reg */
1150 	PHY_MARV_EXT_STAT	= 0x0f,/* 16 bit r/o	Extended Status Reg */
1151 	PHY_MARV_PHY_CTRL	= 0x10,/* 16 bit r/w	PHY Specific Ctrl Reg */
1152 	PHY_MARV_PHY_STAT	= 0x11,/* 16 bit r/o	PHY Specific Stat Reg */
1153 	PHY_MARV_INT_MASK	= 0x12,/* 16 bit r/w	Interrupt Mask Reg */
1154 	PHY_MARV_INT_STAT	= 0x13,/* 16 bit r/o	Interrupt Status Reg */
1155 	PHY_MARV_EXT_CTRL	= 0x14,/* 16 bit r/w	Ext. PHY Specific Ctrl */
1156 	PHY_MARV_RXE_CNT	= 0x15,/* 16 bit r/w	Receive Error Counter */
1157 	PHY_MARV_EXT_ADR	= 0x16,/* 16 bit r/w	Ext. Ad. for Cable Diag. */
1158 	PHY_MARV_PORT_IRQ	= 0x17,/* 16 bit r/o	Port 0 IRQ (88E1111 only) */
1159 	PHY_MARV_LED_CTRL	= 0x18,/* 16 bit r/w	LED Control Reg */
1160 	PHY_MARV_LED_OVER	= 0x19,/* 16 bit r/w	Manual LED Override Reg */
1161 	PHY_MARV_EXT_CTRL_2	= 0x1a,/* 16 bit r/w	Ext. PHY Specific Ctrl 2 */
1162 	PHY_MARV_EXT_P_STAT	= 0x1b,/* 16 bit r/w	Ext. PHY Spec. Stat Reg */
1163 	PHY_MARV_CABLE_DIAG	= 0x1c,/* 16 bit r/o	Cable Diagnostic Reg */
1164 	PHY_MARV_PAGE_ADDR	= 0x1d,/* 16 bit r/w	Extended Page Address Reg */
1165 	PHY_MARV_PAGE_DATA	= 0x1e,/* 16 bit r/w	Extended Page Data Reg */
1166 
1167 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1168 	PHY_MARV_FE_LED_PAR	= 0x16,/* 16 bit r/w	LED Parallel Select Reg. */
1169 	PHY_MARV_FE_LED_SER	= 0x17,/* 16 bit r/w	LED Stream Select S. LED */
1170 	PHY_MARV_FE_VCT_TX	= 0x1a,/* 16 bit r/w	VCT Reg. for TXP/N Pins */
1171 	PHY_MARV_FE_VCT_RX	= 0x1b,/* 16 bit r/o	VCT Reg. for RXP/N Pins */
1172 	PHY_MARV_FE_SPEC_2	= 0x1c,/* 16 bit r/w	Specific Control Reg. 2 */
1173 };
1174 
1175 enum {
1176 	PHY_CT_RESET	= 1<<15, /* Bit 15: (sc)	clear all PHY related regs */
1177 	PHY_CT_LOOP	= 1<<14, /* Bit 14:	enable Loopback over PHY */
1178 	PHY_CT_SPS_LSB	= 1<<13, /* Bit 13:	Speed select, lower bit */
1179 	PHY_CT_ANE	= 1<<12, /* Bit 12:	Auto-Negotiation Enabled */
1180 	PHY_CT_PDOWN	= 1<<11, /* Bit 11:	Power Down Mode */
1181 	PHY_CT_ISOL	= 1<<10, /* Bit 10:	Isolate Mode */
1182 	PHY_CT_RE_CFG	= 1<<9, /* Bit  9:	(sc) Restart Auto-Negotiation */
1183 	PHY_CT_DUP_MD	= 1<<8, /* Bit  8:	Duplex Mode */
1184 	PHY_CT_COL_TST	= 1<<7, /* Bit  7:	Collision Test enabled */
1185 	PHY_CT_SPS_MSB	= 1<<6, /* Bit  6:	Speed select, upper bit */
1186 };
1187 
1188 enum {
1189 	PHY_CT_SP1000	= PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1190 	PHY_CT_SP100	= PHY_CT_SPS_LSB, /* enable speed of  100 Mbps */
1191 	PHY_CT_SP10	= 0,		  /* enable speed of   10 Mbps */
1192 };
1193 
1194 enum {
1195 	PHY_ST_EXT_ST	= 1<<8, /* Bit  8:	Extended Status Present */
1196 
1197 	PHY_ST_PRE_SUP	= 1<<6, /* Bit  6:	Preamble Suppression */
1198 	PHY_ST_AN_OVER	= 1<<5, /* Bit  5:	Auto-Negotiation Over */
1199 	PHY_ST_REM_FLT	= 1<<4, /* Bit  4:	Remote Fault Condition Occurred */
1200 	PHY_ST_AN_CAP	= 1<<3, /* Bit  3:	Auto-Negotiation Capability */
1201 	PHY_ST_LSYNC	= 1<<2, /* Bit  2:	Link Synchronized */
1202 	PHY_ST_JAB_DET	= 1<<1, /* Bit  1:	Jabber Detected */
1203 	PHY_ST_EXT_REG	= 1<<0, /* Bit  0:	Extended Register available */
1204 };
1205 
1206 enum {
1207 	PHY_I1_OUI_MSK	= 0x3f<<10, /* Bit 15..10:	Organization Unique ID */
1208 	PHY_I1_MOD_NUM	= 0x3f<<4, /* Bit  9.. 4:	Model Number */
1209 	PHY_I1_REV_MSK	= 0xf, /* Bit  3.. 0:	Revision Number */
1210 };
1211 
1212 /* different Marvell PHY Ids */
1213 enum {
1214 	PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1215 
1216 	PHY_BCOM_ID1_A1	= 0x6041,
1217 	PHY_BCOM_ID1_B2	= 0x6043,
1218 	PHY_BCOM_ID1_C0	= 0x6044,
1219 	PHY_BCOM_ID1_C5	= 0x6047,
1220 
1221 	PHY_MARV_ID1_B0	= 0x0C23, /* Yukon 	(PHY 88E1011) */
1222 	PHY_MARV_ID1_B2	= 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1223 	PHY_MARV_ID1_C2	= 0x0CC2, /* Yukon-EC	(PHY 88E1111) */
1224 	PHY_MARV_ID1_Y2	= 0x0C91, /* Yukon-2	(PHY 88E1112) */
1225 	PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE   (PHY 88E3082 Rev.A1) */
1226 	PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU  (PHY 88E1149 Rev.B2?) */
1227 };
1228 
1229 /* Advertisement register bits */
1230 enum {
1231 	PHY_AN_NXT_PG	= 1<<15, /* Bit 15:	Request Next Page */
1232 	PHY_AN_ACK	= 1<<14, /* Bit 14:	(ro) Acknowledge Received */
1233 	PHY_AN_RF	= 1<<13, /* Bit 13:	Remote Fault Bits */
1234 
1235 	PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11:	Try for asymmetric */
1236 	PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10:	Try for pause */
1237 	PHY_AN_100BASE4	= 1<<9, /* Bit 9:	Try for 100mbps 4k packets */
1238 	PHY_AN_100FULL	= 1<<8, /* Bit 8:	Try for 100mbps full-duplex */
1239 	PHY_AN_100HALF	= 1<<7, /* Bit 7:	Try for 100mbps half-duplex */
1240 	PHY_AN_10FULL	= 1<<6, /* Bit 6:	Try for 10mbps full-duplex */
1241 	PHY_AN_10HALF	= 1<<5, /* Bit 5:	Try for 10mbps half-duplex */
1242 	PHY_AN_CSMA	= 1<<0, /* Bit 0:	Only selector supported */
1243 	PHY_AN_SEL	= 0x1f, /* Bit 4..0:	Selector Field, 00001=Ethernet*/
1244 	PHY_AN_FULL	= PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1245 	PHY_AN_ALL	= PHY_AN_10HALF | PHY_AN_10FULL |
1246 		  	  PHY_AN_100HALF | PHY_AN_100FULL,
1247 };
1248 
1249 /*****  PHY_BCOM_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
1250 /*****  PHY_MARV_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
1251 enum {
1252 	PHY_B_1000S_MSF	= 1<<15, /* Bit 15:	Master/Slave Fault */
1253 	PHY_B_1000S_MSR	= 1<<14, /* Bit 14:	Master/Slave Result */
1254 	PHY_B_1000S_LRS	= 1<<13, /* Bit 13:	Local Receiver Status */
1255 	PHY_B_1000S_RRS	= 1<<12, /* Bit 12:	Remote Receiver Status */
1256 	PHY_B_1000S_LP_FD	= 1<<11, /* Bit 11:	Link Partner can FD */
1257 	PHY_B_1000S_LP_HD	= 1<<10, /* Bit 10:	Link Partner can HD */
1258 									/* Bit  9..8:	reserved */
1259 	PHY_B_1000S_IEC	= 0xff, /* Bit  7..0:	Idle Error Count */
1260 };
1261 
1262 /** Marvell-Specific */
1263 enum {
1264 	PHY_M_AN_NXT_PG	= 1<<15, /* Request Next Page */
1265 	PHY_M_AN_ACK	= 1<<14, /* (ro)	Acknowledge Received */
1266 	PHY_M_AN_RF	= 1<<13, /* Remote Fault */
1267 
1268 	PHY_M_AN_ASP	= 1<<11, /* Asymmetric Pause */
1269 	PHY_M_AN_PC	= 1<<10, /* MAC Pause implemented */
1270 	PHY_M_AN_100_T4	= 1<<9, /* Not cap. 100Base-T4 (always 0) */
1271 	PHY_M_AN_100_FD	= 1<<8, /* Advertise 100Base-TX Full Duplex */
1272 	PHY_M_AN_100_HD	= 1<<7, /* Advertise 100Base-TX Half Duplex */
1273 	PHY_M_AN_10_FD	= 1<<6, /* Advertise 10Base-TX Full Duplex */
1274 	PHY_M_AN_10_HD	= 1<<5, /* Advertise 10Base-TX Half Duplex */
1275 	PHY_M_AN_SEL_MSK =0x1f<<4,	/* Bit  4.. 0: Selector Field Mask */
1276 };
1277 
1278 /* special defines for FIBER (88E1011S only) */
1279 enum {
1280 	PHY_M_AN_ASP_X	= 1<<8, /* Asymmetric Pause */
1281 	PHY_M_AN_PC_X	= 1<<7, /* MAC Pause implemented */
1282 	PHY_M_AN_1000X_AHD	= 1<<6, /* Advertise 10000Base-X Half Duplex */
1283 	PHY_M_AN_1000X_AFD	= 1<<5, /* Advertise 10000Base-X Full Duplex */
1284 };
1285 
1286 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1287 enum {
1288 	PHY_M_P_NO_PAUSE_X	= 0<<7,/* Bit  8.. 7:	no Pause Mode */
1289 	PHY_M_P_SYM_MD_X	= 1<<7, /* Bit  8.. 7:	symmetric Pause Mode */
1290 	PHY_M_P_ASYM_MD_X	= 2<<7,/* Bit  8.. 7:	asymmetric Pause Mode */
1291 	PHY_M_P_BOTH_MD_X	= 3<<7,/* Bit  8.. 7:	both Pause Mode */
1292 };
1293 
1294 /*****  PHY_MARV_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/
1295 enum {
1296 	PHY_M_1000C_TEST	= 7<<13,/* Bit 15..13:	Test Modes */
1297 	PHY_M_1000C_MSE	= 1<<12, /* Manual Master/Slave Enable */
1298 	PHY_M_1000C_MSC	= 1<<11, /* M/S Configuration (1=Master) */
1299 	PHY_M_1000C_MPD	= 1<<10, /* Multi-Port Device */
1300 	PHY_M_1000C_AFD	= 1<<9, /* Advertise Full Duplex */
1301 	PHY_M_1000C_AHD	= 1<<8, /* Advertise Half Duplex */
1302 };
1303 
1304 /*****  PHY_MARV_PHY_CTRL	16 bit r/w	PHY Specific Ctrl Reg *****/
1305 enum {
1306 	PHY_M_PC_TX_FFD_MSK	= 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1307 	PHY_M_PC_RX_FFD_MSK	= 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1308 	PHY_M_PC_ASS_CRS_TX	= 1<<11, /* Assert CRS on Transmit */
1309 	PHY_M_PC_FL_GOOD	= 1<<10, /* Force Link Good */
1310 	PHY_M_PC_EN_DET_MSK	= 3<<8,/* Bit  9.. 8: Energy Detect Mask */
1311 	PHY_M_PC_ENA_EXT_D	= 1<<7, /* Enable Ext. Distance (10BT) */
1312 	PHY_M_PC_MDIX_MSK	= 3<<5,/* Bit  6.. 5: MDI/MDIX Config. Mask */
1313 	PHY_M_PC_DIS_125CLK	= 1<<4, /* Disable 125 CLK */
1314 	PHY_M_PC_MAC_POW_UP	= 1<<3, /* MAC Power up */
1315 	PHY_M_PC_SQE_T_ENA	= 1<<2, /* SQE Test Enabled */
1316 	PHY_M_PC_POL_R_DIS	= 1<<1, /* Polarity Reversal Disabled */
1317 	PHY_M_PC_DIS_JABBER	= 1<<0, /* Disable Jabber */
1318 };
1319 
1320 enum {
1321 	PHY_M_PC_EN_DET		= 2<<8,	/* Energy Detect (Mode 1) */
1322 	PHY_M_PC_EN_DET_PLUS	= 3<<8, /* Energy Detect Plus (Mode 2) */
1323 };
1324 
1325 #define PHY_M_PC_MDI_XMODE(x)	(((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
1326 
1327 enum {
1328 	PHY_M_PC_MAN_MDI	= 0, /* 00 = Manual MDI configuration */
1329 	PHY_M_PC_MAN_MDIX	= 1, /* 01 = Manual MDIX configuration */
1330 	PHY_M_PC_ENA_AUTO	= 3, /* 11 = Enable Automatic Crossover */
1331 };
1332 
1333 /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
1334 enum {
1335 	PHY_M_PC_COP_TX_DIS	= 1<<3, /* Copper Transmitter Disable */
1336 	PHY_M_PC_POW_D_ENA	= 1<<2,	/* Power Down Enable */
1337 };
1338 
1339 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1340 enum {
1341 	PHY_M_PC_ENA_DTE_DT	= 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1342 	PHY_M_PC_ENA_ENE_DT	= 1<<14, /* Enable Energy Detect (sense & pulse) */
1343 	PHY_M_PC_DIS_NLP_CK	= 1<<13, /* Disable Normal Link Puls (NLP) Check */
1344 	PHY_M_PC_ENA_LIP_NP	= 1<<12, /* Enable Link Partner Next Page Reg. */
1345 	PHY_M_PC_DIS_NLP_GN	= 1<<11, /* Disable Normal Link Puls Generation */
1346 
1347 	PHY_M_PC_DIS_SCRAMB	= 1<<9, /* Disable Scrambler */
1348 	PHY_M_PC_DIS_FEFI	= 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1349 
1350 	PHY_M_PC_SH_TP_SEL	= 1<<6, /* Shielded Twisted Pair Select */
1351 	PHY_M_PC_RX_FD_MSK	= 3<<2,/* Bit  3.. 2: Rx FIFO Depth Mask */
1352 };
1353 
1354 /*****  PHY_MARV_PHY_STAT	16 bit r/o	PHY Specific Status Reg *****/
1355 enum {
1356 	PHY_M_PS_SPEED_MSK	= 3<<14, /* Bit 15..14: Speed Mask */
1357 	PHY_M_PS_SPEED_1000	= 1<<15, /*		10 = 1000 Mbps */
1358 	PHY_M_PS_SPEED_100	= 1<<14, /*		01 =  100 Mbps */
1359 	PHY_M_PS_SPEED_10	= 0,	 /*		00 =   10 Mbps */
1360 	PHY_M_PS_FULL_DUP	= 1<<13, /* Full Duplex */
1361 	PHY_M_PS_PAGE_REC	= 1<<12, /* Page Received */
1362 	PHY_M_PS_SPDUP_RES	= 1<<11, /* Speed & Duplex Resolved */
1363 	PHY_M_PS_LINK_UP	= 1<<10, /* Link Up */
1364 	PHY_M_PS_CABLE_MSK	= 7<<7,  /* Bit  9.. 7: Cable Length Mask */
1365 	PHY_M_PS_MDI_X_STAT	= 1<<6,  /* MDI Crossover Stat (1=MDIX) */
1366 	PHY_M_PS_DOWNS_STAT	= 1<<5,  /* Downshift Status (1=downsh.) */
1367 	PHY_M_PS_ENDET_STAT	= 1<<4,  /* Energy Detect Status (1=act) */
1368 	PHY_M_PS_TX_P_EN	= 1<<3,  /* Tx Pause Enabled */
1369 	PHY_M_PS_RX_P_EN	= 1<<2,  /* Rx Pause Enabled */
1370 	PHY_M_PS_POL_REV	= 1<<1,  /* Polarity Reversed */
1371 	PHY_M_PS_JABBER		= 1<<0,  /* Jabber */
1372 };
1373 
1374 #define PHY_M_PS_PAUSE_MSK	(PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1375 
1376 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1377 enum {
1378 	PHY_M_PS_DTE_DETECT	= 1<<15, /* Data Terminal Equipment (DTE) Detected */
1379 	PHY_M_PS_RES_SPEED	= 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1380 };
1381 
1382 enum {
1383 	PHY_M_IS_AN_ERROR	= 1<<15, /* Auto-Negotiation Error */
1384 	PHY_M_IS_LSP_CHANGE	= 1<<14, /* Link Speed Changed */
1385 	PHY_M_IS_DUP_CHANGE	= 1<<13, /* Duplex Mode Changed */
1386 	PHY_M_IS_AN_PR		= 1<<12, /* Page Received */
1387 	PHY_M_IS_AN_COMPL	= 1<<11, /* Auto-Negotiation Completed */
1388 	PHY_M_IS_LST_CHANGE	= 1<<10, /* Link Status Changed */
1389 	PHY_M_IS_SYMB_ERROR	= 1<<9, /* Symbol Error */
1390 	PHY_M_IS_FALSE_CARR	= 1<<8, /* False Carrier */
1391 	PHY_M_IS_FIFO_ERROR	= 1<<7, /* FIFO Overflow/Underrun Error */
1392 	PHY_M_IS_MDI_CHANGE	= 1<<6, /* MDI Crossover Changed */
1393 	PHY_M_IS_DOWNSH_DET	= 1<<5, /* Downshift Detected */
1394 	PHY_M_IS_END_CHANGE	= 1<<4, /* Energy Detect Changed */
1395 
1396 	PHY_M_IS_DTE_CHANGE	= 1<<2, /* DTE Power Det. Status Changed */
1397 	PHY_M_IS_POL_CHANGE	= 1<<1, /* Polarity Changed */
1398 	PHY_M_IS_JABBER		= 1<<0, /* Jabber */
1399 
1400 	PHY_M_DEF_MSK		= PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1401 				 | PHY_M_IS_DUP_CHANGE,
1402 	PHY_M_AN_MSK	       = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1403 };
1404 
1405 
1406 /*****  PHY_MARV_EXT_CTRL	16 bit r/w	Ext. PHY Specific Ctrl *****/
1407 enum {
1408 	PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1409 	PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1410 
1411 	PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1412 	PHY_M_EC_M_DSC_MSK  = 3<<10, /* Bit 11..10:	Master Downshift Counter */
1413 					/* (88E1011 only) */
1414 	PHY_M_EC_S_DSC_MSK  = 3<<8,/* Bit  9.. 8:	Slave  Downshift Counter */
1415 				       /* (88E1011 only) */
1416 	PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9:	Master Downshift Counter */
1417 					/* (88E1111 only) */
1418 	PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1419 					/* !!! Errata in spec. (1 = disable) */
1420 	PHY_M_EC_RX_TIM_CT  = 1<<7, /* RGMII Rx Timing Control*/
1421 	PHY_M_EC_MAC_S_MSK  = 7<<4,/* Bit  6.. 4:	Def. MAC interface speed */
1422 	PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1423 	PHY_M_EC_DTE_D_ENA  = 1<<2, /* DTE Detect Enable (88E1111 only) */
1424 	PHY_M_EC_TX_TIM_CT  = 1<<1, /* RGMII Tx Timing Control */
1425 	PHY_M_EC_TRANS_DIS  = 1<<0, /* Transmitter Disable (88E1111 only) */
1426 
1427 	PHY_M_10B_TE_ENABLE = 1<<7, /* 10Base-Te Enable (88E8079 and above) */
1428 };
1429 #define PHY_M_EC_M_DSC(x)	((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
1430 					/* 00=1x; 01=2x; 10=3x; 11=4x */
1431 #define PHY_M_EC_S_DSC(x)	((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
1432 					/* 00=dis; 01=1x; 10=2x; 11=3x */
1433 #define PHY_M_EC_DSC_2(x)	((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
1434 					/* 000=1x; 001=2x; 010=3x; 011=4x */
1435 #define PHY_M_EC_MAC_S(x)	((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
1436 					/* 01X=0; 110=2.5; 111=25 (MHz) */
1437 
1438 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1439 enum {
1440 	PHY_M_PC_DIS_LINK_Pa	= 1<<15,/* Disable Link Pulses */
1441 	PHY_M_PC_DSC_MSK	= 7<<12,/* Bit 14..12:	Downshift Counter */
1442 	PHY_M_PC_DOWN_S_ENA	= 1<<11,/* Downshift Enable */
1443 };
1444 /* !!! Errata in spec. (1 = disable) */
1445 
1446 #define PHY_M_PC_DSC(x)			(((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
1447 											/* 100=5x; 101=6x; 110=7x; 111=8x */
1448 enum {
1449 	MAC_TX_CLK_0_MHZ	= 2,
1450 	MAC_TX_CLK_2_5_MHZ	= 6,
1451 	MAC_TX_CLK_25_MHZ 	= 7,
1452 };
1453 
1454 /*****  PHY_MARV_LED_CTRL	16 bit r/w	LED Control Reg *****/
1455 enum {
1456 	PHY_M_LEDC_DIS_LED	= 1<<15, /* Disable LED */
1457 	PHY_M_LEDC_PULS_MSK	= 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1458 	PHY_M_LEDC_F_INT	= 1<<11, /* Force Interrupt */
1459 	PHY_M_LEDC_BL_R_MSK	= 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1460 	PHY_M_LEDC_DP_C_LSB	= 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1461 	PHY_M_LEDC_TX_C_LSB	= 1<<6, /* Tx Control (LSB, 88E1111 only) */
1462 	PHY_M_LEDC_LK_C_MSK	= 7<<3,/* Bit  5.. 3: Link Control Mask */
1463 					/* (88E1111 only) */
1464 };
1465 
1466 enum {
1467 	PHY_M_LEDC_LINK_MSK	= 3<<3,/* Bit  4.. 3: Link Control Mask */
1468 									/* (88E1011 only) */
1469 	PHY_M_LEDC_DP_CTRL	= 1<<2, /* Duplex Control */
1470 	PHY_M_LEDC_DP_C_MSB	= 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1471 	PHY_M_LEDC_RX_CTRL	= 1<<1, /* Rx Activity / Link */
1472 	PHY_M_LEDC_TX_CTRL	= 1<<0, /* Tx Activity / Link */
1473 	PHY_M_LEDC_TX_C_MSB	= 1<<0, /* Tx Control (MSB, 88E1111 only) */
1474 };
1475 
1476 #define PHY_M_LED_PULS_DUR(x)	(((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1477 
1478 /*****  PHY_MARV_PHY_STAT (page 3)16 bit r/w	Polarity Control Reg. *****/
1479 enum {
1480 	PHY_M_POLC_LS1M_MSK	= 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1481 	PHY_M_POLC_IS0M_MSK	= 0xf<<8,  /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1482 	PHY_M_POLC_LOS_MSK	= 0x3<<6,  /* Bit  7.. 6: LOS Pol. Ctrl. Mask */
1483 	PHY_M_POLC_INIT_MSK	= 0x3<<4,  /* Bit  5.. 4: INIT Pol. Ctrl. Mask */
1484 	PHY_M_POLC_STA1_MSK	= 0x3<<2,  /* Bit  3.. 2: STAT1 Pol. Ctrl. Mask */
1485 	PHY_M_POLC_STA0_MSK	= 0x3,     /* Bit  1.. 0: STAT0 Pol. Ctrl. Mask */
1486 };
1487 
1488 #define PHY_M_POLC_LS1_P_MIX(x)	(((x)<<12) & PHY_M_POLC_LS1M_MSK)
1489 #define PHY_M_POLC_IS0_P_MIX(x)	(((x)<<8) & PHY_M_POLC_IS0M_MSK)
1490 #define PHY_M_POLC_LOS_CTRL(x)	(((x)<<6) & PHY_M_POLC_LOS_MSK)
1491 #define PHY_M_POLC_INIT_CTRL(x)	(((x)<<4) & PHY_M_POLC_INIT_MSK)
1492 #define PHY_M_POLC_STA1_CTRL(x)	(((x)<<2) & PHY_M_POLC_STA1_MSK)
1493 #define PHY_M_POLC_STA0_CTRL(x)	(((x)<<0) & PHY_M_POLC_STA0_MSK)
1494 
1495 enum {
1496 	PULS_NO_STR	= 0,/* no pulse stretching */
1497 	PULS_21MS	= 1,/* 21 ms to 42 ms */
1498 	PULS_42MS	= 2,/* 42 ms to 84 ms */
1499 	PULS_84MS	= 3,/* 84 ms to 170 ms */
1500 	PULS_170MS	= 4,/* 170 ms to 340 ms */
1501 	PULS_340MS	= 5,/* 340 ms to 670 ms */
1502 	PULS_670MS	= 6,/* 670 ms to 1.3 s */
1503 	PULS_1300MS	= 7,/* 1.3 s to 2.7 s */
1504 };
1505 
1506 #define PHY_M_LED_BLINK_RT(x)	(((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1507 
1508 enum {
1509 	BLINK_42MS	= 0,/* 42 ms */
1510 	BLINK_84MS	= 1,/* 84 ms */
1511 	BLINK_170MS	= 2,/* 170 ms */
1512 	BLINK_340MS	= 3,/* 340 ms */
1513 	BLINK_670MS	= 4,/* 670 ms */
1514 };
1515 
1516 /*****  PHY_MARV_LED_OVER	16 bit r/w	Manual LED Override Reg *****/
1517 #define PHY_M_LED_MO_SGMII(x)	((x)<<14)	/* Bit 15..14:  SGMII AN Timer */
1518 
1519 #define PHY_M_LED_MO_DUP(x)	((x)<<10)	/* Bit 11..10:  Duplex */
1520 #define PHY_M_LED_MO_10(x)	((x)<<8)	/* Bit  9.. 8:  Link 10 */
1521 #define PHY_M_LED_MO_100(x)	((x)<<6)	/* Bit  7.. 6:  Link 100 */
1522 #define PHY_M_LED_MO_1000(x)	((x)<<4)	/* Bit  5.. 4:  Link 1000 */
1523 #define PHY_M_LED_MO_RX(x)	((x)<<2)	/* Bit  3.. 2:  Rx */
1524 #define PHY_M_LED_MO_TX(x)	((x)<<0)	/* Bit  1.. 0:  Tx */
1525 
1526 enum led_mode {
1527 	MO_LED_NORM  = 0,
1528 	MO_LED_BLINK = 1,
1529 	MO_LED_OFF   = 2,
1530 	MO_LED_ON    = 3,
1531 };
1532 
1533 /*****  PHY_MARV_EXT_CTRL_2	16 bit r/w	Ext. PHY Specific Ctrl 2 *****/
1534 enum {
1535 	PHY_M_EC2_FI_IMPED	= 1<<6, /* Fiber Input  Impedance */
1536 	PHY_M_EC2_FO_IMPED	= 1<<5, /* Fiber Output Impedance */
1537 	PHY_M_EC2_FO_M_CLK	= 1<<4, /* Fiber Mode Clock Enable */
1538 	PHY_M_EC2_FO_BOOST	= 1<<3, /* Fiber Output Boost */
1539 	PHY_M_EC2_FO_AM_MSK	= 7,/* Bit  2.. 0:	Fiber Output Amplitude */
1540 };
1541 
1542 /*****  PHY_MARV_EXT_P_STAT 16 bit r/w	Ext. PHY Specific Status *****/
1543 enum {
1544 	PHY_M_FC_AUTO_SEL	= 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1545 	PHY_M_FC_AN_REG_ACC	= 1<<14, /* Fiber/Copper AN Reg. Access */
1546 	PHY_M_FC_RESOLUTION	= 1<<13, /* Fiber/Copper Resolution */
1547 	PHY_M_SER_IF_AN_BP	= 1<<12, /* Ser. IF AN Bypass Enable */
1548 	PHY_M_SER_IF_BP_ST	= 1<<11, /* Ser. IF AN Bypass Status */
1549 	PHY_M_IRQ_POLARITY	= 1<<10, /* IRQ polarity */
1550 	PHY_M_DIS_AUT_MED	= 1<<9, /* Disable Aut. Medium Reg. Selection */
1551 	/* (88E1111 only) */
1552 
1553 	PHY_M_UNDOC1		= 1<<7, /* undocumented bit !! */
1554 	PHY_M_DTE_POW_STAT	= 1<<4, /* DTE Power Status (88E1111 only) */
1555 	PHY_M_MODE_MASK	= 0xf, /* Bit  3.. 0: copy of HWCFG MODE[3:0] */
1556 };
1557 
1558 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1559 /*****  PHY_MARV_FE_LED_PAR		16 bit r/w	LED Parallel Select Reg. *****/
1560 									/* Bit 15..12: reserved (used internally) */
1561 enum {
1562 	PHY_M_FELP_LED2_MSK = 0xf<<8,	/* Bit 11.. 8: LED2 Mask (LINK) */
1563 	PHY_M_FELP_LED1_MSK = 0xf<<4,	/* Bit  7.. 4: LED1 Mask (ACT) */
1564 	PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */
1565 };
1566 
1567 #define PHY_M_FELP_LED2_CTRL(x)	(((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
1568 #define PHY_M_FELP_LED1_CTRL(x)	(((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
1569 #define PHY_M_FELP_LED0_CTRL(x)	(((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
1570 
1571 enum {
1572 	LED_PAR_CTRL_COLX	= 0x00,
1573 	LED_PAR_CTRL_ERROR	= 0x01,
1574 	LED_PAR_CTRL_DUPLEX	= 0x02,
1575 	LED_PAR_CTRL_DP_COL	= 0x03,
1576 	LED_PAR_CTRL_SPEED	= 0x04,
1577 	LED_PAR_CTRL_LINK	= 0x05,
1578 	LED_PAR_CTRL_TX		= 0x06,
1579 	LED_PAR_CTRL_RX		= 0x07,
1580 	LED_PAR_CTRL_ACT	= 0x08,
1581 	LED_PAR_CTRL_LNK_RX	= 0x09,
1582 	LED_PAR_CTRL_LNK_AC	= 0x0a,
1583 	LED_PAR_CTRL_ACT_BL	= 0x0b,
1584 	LED_PAR_CTRL_TX_BL	= 0x0c,
1585 	LED_PAR_CTRL_RX_BL	= 0x0d,
1586 	LED_PAR_CTRL_COL_BL	= 0x0e,
1587 	LED_PAR_CTRL_INACT	= 0x0f
1588 };
1589 
1590 /*****,PHY_MARV_FE_SPEC_2		16 bit r/w	Specific Control Reg. 2 *****/
1591 enum {
1592 	PHY_M_FESC_DIS_WAIT	= 1<<2, /* Disable TDR Waiting Period */
1593 	PHY_M_FESC_ENA_MCLK	= 1<<1, /* Enable MAC Rx Clock in sleep mode */
1594 	PHY_M_FESC_SEL_CL_A	= 1<<0, /* Select Class A driver (100B-TX) */
1595 };
1596 
1597 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1598 /*****  PHY_MARV_PHY_CTRL (page 1)		16 bit r/w	Fiber Specific Ctrl *****/
1599 enum {
1600 	PHY_M_FIB_FORCE_LNK	= 1<<10,/* Force Link Good */
1601 	PHY_M_FIB_SIGD_POL	= 1<<9,	/* SIGDET Polarity */
1602 	PHY_M_FIB_TX_DIS	= 1<<3,	/* Transmitter Disable */
1603 };
1604 
1605 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1606 /*****  PHY_MARV_PHY_CTRL (page 2)		16 bit r/w	MAC Specific Ctrl *****/
1607 enum {
1608 	PHY_M_MAC_MD_MSK	= 7<<7, /* Bit  9.. 7: Mode Select Mask */
1609 	PHY_M_MAC_GMIF_PUP	= 1<<3,	/* GMII Power Up (88E1149 only) */
1610 	PHY_M_MAC_MD_AUTO	= 3,/* Auto Copper/1000Base-X */
1611 	PHY_M_MAC_MD_COPPER	= 5,/* Copper only */
1612 	PHY_M_MAC_MD_1000BX	= 7,/* 1000Base-X only */
1613 };
1614 #define PHY_M_MAC_MODE_SEL(x)	(((x)<<7) & PHY_M_MAC_MD_MSK)
1615 
1616 /*****  PHY_MARV_PHY_CTRL (page 3)		16 bit r/w	LED Control Reg. *****/
1617 enum {
1618 	PHY_M_LEDC_LOS_MSK	= 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1619 	PHY_M_LEDC_INIT_MSK	= 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1620 	PHY_M_LEDC_STA1_MSK	= 0xf<<4,/* Bit  7.. 4: STAT1 LED Ctrl. Mask */
1621 	PHY_M_LEDC_STA0_MSK	= 0xf, /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
1622 };
1623 
1624 #define PHY_M_LEDC_LOS_CTRL(x)	(((x)<<12) & PHY_M_LEDC_LOS_MSK)
1625 #define PHY_M_LEDC_INIT_CTRL(x)	(((x)<<8) & PHY_M_LEDC_INIT_MSK)
1626 #define PHY_M_LEDC_STA1_CTRL(x)	(((x)<<4) & PHY_M_LEDC_STA1_MSK)
1627 #define PHY_M_LEDC_STA0_CTRL(x)	(((x)<<0) & PHY_M_LEDC_STA0_MSK)
1628 
1629 /* GMAC registers  */
1630 /* Port Registers */
1631 enum {
1632 	GM_GP_STAT	= 0x0000,	/* 16 bit r/o	General Purpose Status */
1633 	GM_GP_CTRL	= 0x0004,	/* 16 bit r/w	General Purpose Control */
1634 	GM_TX_CTRL	= 0x0008,	/* 16 bit r/w	Transmit Control Reg. */
1635 	GM_RX_CTRL	= 0x000c,	/* 16 bit r/w	Receive Control Reg. */
1636 	GM_TX_FLOW_CTRL	= 0x0010,	/* 16 bit r/w	Transmit Flow-Control */
1637 	GM_TX_PARAM	= 0x0014,	/* 16 bit r/w	Transmit Parameter Reg. */
1638 	GM_SERIAL_MODE	= 0x0018,	/* 16 bit r/w	Serial Mode Register */
1639 /* Source Address Registers */
1640 	GM_SRC_ADDR_1L	= 0x001c,	/* 16 bit r/w	Source Address 1 (low) */
1641 	GM_SRC_ADDR_1M	= 0x0020,	/* 16 bit r/w	Source Address 1 (middle) */
1642 	GM_SRC_ADDR_1H	= 0x0024,	/* 16 bit r/w	Source Address 1 (high) */
1643 	GM_SRC_ADDR_2L	= 0x0028,	/* 16 bit r/w	Source Address 2 (low) */
1644 	GM_SRC_ADDR_2M	= 0x002c,	/* 16 bit r/w	Source Address 2 (middle) */
1645 	GM_SRC_ADDR_2H	= 0x0030,	/* 16 bit r/w	Source Address 2 (high) */
1646 
1647 /* Multicast Address Hash Registers */
1648 	GM_MC_ADDR_H1	= 0x0034,	/* 16 bit r/w	Multicast Address Hash 1 */
1649 	GM_MC_ADDR_H2	= 0x0038,	/* 16 bit r/w	Multicast Address Hash 2 */
1650 	GM_MC_ADDR_H3	= 0x003c,	/* 16 bit r/w	Multicast Address Hash 3 */
1651 	GM_MC_ADDR_H4	= 0x0040,	/* 16 bit r/w	Multicast Address Hash 4 */
1652 
1653 /* Interrupt Source Registers */
1654 	GM_TX_IRQ_SRC	= 0x0044,	/* 16 bit r/o	Tx Overflow IRQ Source */
1655 	GM_RX_IRQ_SRC	= 0x0048,	/* 16 bit r/o	Rx Overflow IRQ Source */
1656 	GM_TR_IRQ_SRC	= 0x004c,	/* 16 bit r/o	Tx/Rx Over. IRQ Source */
1657 
1658 /* Interrupt Mask Registers */
1659 	GM_TX_IRQ_MSK	= 0x0050,	/* 16 bit r/w	Tx Overflow IRQ Mask */
1660 	GM_RX_IRQ_MSK	= 0x0054,	/* 16 bit r/w	Rx Overflow IRQ Mask */
1661 	GM_TR_IRQ_MSK	= 0x0058,	/* 16 bit r/w	Tx/Rx Over. IRQ Mask */
1662 
1663 /* Serial Management Interface (SMI) Registers */
1664 	GM_SMI_CTRL	= 0x0080,	/* 16 bit r/w	SMI Control Register */
1665 	GM_SMI_DATA	= 0x0084,	/* 16 bit r/w	SMI Data Register */
1666 	GM_PHY_ADDR	= 0x0088,	/* 16 bit r/w	GPHY Address Register */
1667 /* MIB Counters */
1668 	GM_MIB_CNT_BASE	= 0x0100,	/* Base Address of MIB Counters */
1669 	GM_MIB_CNT_END	= 0x025C,	/* Last MIB counter */
1670 };
1671 
1672 
1673 /*
1674  * MIB Counters base address definitions (low word) -
1675  * use offset 4 for access to high word	(32 bit r/o)
1676  */
1677 enum {
1678 	GM_RXF_UC_OK    = GM_MIB_CNT_BASE + 0,	/* Unicast Frames Received OK */
1679 	GM_RXF_BC_OK	= GM_MIB_CNT_BASE + 8,	/* Broadcast Frames Received OK */
1680 	GM_RXF_MPAUSE	= GM_MIB_CNT_BASE + 16,	/* Pause MAC Ctrl Frames Received */
1681 	GM_RXF_MC_OK	= GM_MIB_CNT_BASE + 24,	/* Multicast Frames Received OK */
1682 	GM_RXF_FCS_ERR	= GM_MIB_CNT_BASE + 32,	/* Rx Frame Check Seq. Error */
1683 
1684 	GM_RXO_OK_LO	= GM_MIB_CNT_BASE + 48,	/* Octets Received OK Low */
1685 	GM_RXO_OK_HI	= GM_MIB_CNT_BASE + 56,	/* Octets Received OK High */
1686 	GM_RXO_ERR_LO	= GM_MIB_CNT_BASE + 64,	/* Octets Received Invalid Low */
1687 	GM_RXO_ERR_HI	= GM_MIB_CNT_BASE + 72,	/* Octets Received Invalid High */
1688 	GM_RXF_SHT	= GM_MIB_CNT_BASE + 80,	/* Frames <64 Byte Received OK */
1689 	GM_RXE_FRAG	= GM_MIB_CNT_BASE + 88,	/* Frames <64 Byte Received with FCS Err */
1690 	GM_RXF_64B	= GM_MIB_CNT_BASE + 96,	/* 64 Byte Rx Frame */
1691 	GM_RXF_127B	= GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1692 	GM_RXF_255B	= GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1693 	GM_RXF_511B	= GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1694 	GM_RXF_1023B	= GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1695 	GM_RXF_1518B	= GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1696 	GM_RXF_MAX_SZ	= GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1697 	GM_RXF_LNG_ERR	= GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
1698 	GM_RXF_JAB_PKT	= GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
1699 
1700 	GM_RXE_FIFO_OV	= GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
1701 	GM_TXF_UC_OK	= GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
1702 	GM_TXF_BC_OK	= GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
1703 	GM_TXF_MPAUSE	= GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
1704 	GM_TXF_MC_OK	= GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
1705 	GM_TXO_OK_LO	= GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
1706 	GM_TXO_OK_HI	= GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
1707 	GM_TXF_64B	= GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
1708 	GM_TXF_127B	= GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1709 	GM_TXF_255B	= GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1710 	GM_TXF_511B	= GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1711 	GM_TXF_1023B	= GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1712 	GM_TXF_1518B	= GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1713 	GM_TXF_MAX_SZ	= GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1714 
1715 	GM_TXF_COL	= GM_MIB_CNT_BASE + 304,/* Tx Collision */
1716 	GM_TXF_LAT_COL	= GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
1717 	GM_TXF_ABO_COL	= GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
1718 	GM_TXF_MUL_COL	= GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
1719 	GM_TXF_SNG_COL	= GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
1720 	GM_TXE_FIFO_UR	= GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
1721 };
1722 
1723 /* GMAC Bit Definitions */
1724 /*	GM_GP_STAT	16 bit r/o	General Purpose Status Register */
1725 enum {
1726 	GM_GPSR_SPEED		= 1<<15, /* Bit 15:	Port Speed (1 = 100 Mbps) */
1727 	GM_GPSR_DUPLEX		= 1<<14, /* Bit 14:	Duplex Mode (1 = Full) */
1728 	GM_GPSR_FC_TX_DIS	= 1<<13, /* Bit 13:	Tx Flow-Control Mode Disabled */
1729 	GM_GPSR_LINK_UP		= 1<<12, /* Bit 12:	Link Up Status */
1730 	GM_GPSR_PAUSE		= 1<<11, /* Bit 11:	Pause State */
1731 	GM_GPSR_TX_ACTIVE	= 1<<10, /* Bit 10:	Tx in Progress */
1732 	GM_GPSR_EXC_COL		= 1<<9,	/* Bit  9:	Excessive Collisions Occurred */
1733 	GM_GPSR_LAT_COL		= 1<<8,	/* Bit  8:	Late Collisions Occurred */
1734 
1735 	GM_GPSR_PHY_ST_CH	= 1<<5,	/* Bit  5:	PHY Status Change */
1736 	GM_GPSR_GIG_SPEED	= 1<<4,	/* Bit  4:	Gigabit Speed (1 = 1000 Mbps) */
1737 	GM_GPSR_PART_MODE	= 1<<3,	/* Bit  3:	Partition mode */
1738 	GM_GPSR_FC_RX_DIS	= 1<<2,	/* Bit  2:	Rx Flow-Control Mode Disabled */
1739 	GM_GPSR_PROM_EN		= 1<<1,	/* Bit  1:	Promiscuous Mode Enabled */
1740 };
1741 
1742 /*	GM_GP_CTRL	16 bit r/w	General Purpose Control Register */
1743 enum {
1744 	GM_GPCR_PROM_ENA	= 1<<14,	/* Bit 14:	Enable Promiscuous Mode */
1745 	GM_GPCR_FC_TX_DIS	= 1<<13, /* Bit 13:	Disable Tx Flow-Control Mode */
1746 	GM_GPCR_TX_ENA		= 1<<12, /* Bit 12:	Enable Transmit */
1747 	GM_GPCR_RX_ENA		= 1<<11, /* Bit 11:	Enable Receive */
1748 	GM_GPCR_BURST_ENA	= 1<<10, /* Bit 10:	Enable Burst Mode */
1749 	GM_GPCR_LOOP_ENA	= 1<<9,	/* Bit  9:	Enable MAC Loopback Mode */
1750 	GM_GPCR_PART_ENA	= 1<<8,	/* Bit  8:	Enable Partition Mode */
1751 	GM_GPCR_GIGS_ENA	= 1<<7,	/* Bit  7:	Gigabit Speed (1000 Mbps) */
1752 	GM_GPCR_FL_PASS		= 1<<6,	/* Bit  6:	Force Link Pass */
1753 	GM_GPCR_DUP_FULL	= 1<<5,	/* Bit  5:	Full Duplex Mode */
1754 	GM_GPCR_FC_RX_DIS	= 1<<4,	/* Bit  4:	Disable Rx Flow-Control Mode */
1755 	GM_GPCR_SPEED_100	= 1<<3,   /* Bit  3:	Port Speed 100 Mbps */
1756 	GM_GPCR_AU_DUP_DIS	= 1<<2,	/* Bit  2:	Disable Auto-Update Duplex */
1757 	GM_GPCR_AU_FCT_DIS	= 1<<1,	/* Bit  1:	Disable Auto-Update Flow-C. */
1758 	GM_GPCR_AU_SPD_DIS	= 1<<0,	/* Bit  0:	Disable Auto-Update Speed */
1759 };
1760 
1761 #define GM_GPCR_SPEED_1000	(GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1762 
1763 /*	GM_TX_CTRL			16 bit r/w	Transmit Control Register */
1764 enum {
1765 	GM_TXCR_FORCE_JAM	= 1<<15, /* Bit 15:	Force Jam / Flow-Control */
1766 	GM_TXCR_CRC_DIS		= 1<<14, /* Bit 14:	Disable insertion of CRC */
1767 	GM_TXCR_PAD_DIS		= 1<<13, /* Bit 13:	Disable padding of packets */
1768 	GM_TXCR_COL_THR_MSK	= 7<<10, /* Bit 12..10:	Collision Threshold */
1769 };
1770 
1771 #define TX_COL_THR(x)		(((x)<<10) & GM_TXCR_COL_THR_MSK)
1772 #define TX_COL_DEF		0x04
1773 
1774 /*	GM_RX_CTRL			16 bit r/w	Receive Control Register */
1775 enum {
1776 	GM_RXCR_UCF_ENA	= 1<<15, /* Bit 15:	Enable Unicast filtering */
1777 	GM_RXCR_MCF_ENA	= 1<<14, /* Bit 14:	Enable Multicast filtering */
1778 	GM_RXCR_CRC_DIS	= 1<<13, /* Bit 13:	Remove 4-byte CRC */
1779 	GM_RXCR_PASS_FC	= 1<<12, /* Bit 12:	Pass FC packets to FIFO */
1780 };
1781 
1782 /*	GM_TX_PARAM		16 bit r/w	Transmit Parameter Register */
1783 enum {
1784 	GM_TXPA_JAMLEN_MSK	= 0x03<<14,	/* Bit 15..14:	Jam Length */
1785 	GM_TXPA_JAMIPG_MSK	= 0x1f<<9,	/* Bit 13..9:	Jam IPG */
1786 	GM_TXPA_JAMDAT_MSK	= 0x1f<<4,	/* Bit  8..4:	IPG Jam to Data */
1787 	GM_TXPA_BO_LIM_MSK	= 0x0f,		/* Bit  3.. 0: Backoff Limit Mask */
1788 
1789 	TX_JAM_LEN_DEF		= 0x03,
1790 	TX_JAM_IPG_DEF		= 0x0b,
1791 	TX_IPG_JAM_DEF		= 0x1c,
1792 	TX_BOF_LIM_DEF		= 0x04,
1793 };
1794 
1795 #define TX_JAM_LEN_VAL(x)	(((x)<<14) & GM_TXPA_JAMLEN_MSK)
1796 #define TX_JAM_IPG_VAL(x)	(((x)<<9)  & GM_TXPA_JAMIPG_MSK)
1797 #define TX_IPG_JAM_DATA(x)	(((x)<<4)  & GM_TXPA_JAMDAT_MSK)
1798 #define TX_BACK_OFF_LIM(x)	((x) & GM_TXPA_BO_LIM_MSK)
1799 
1800 
1801 /*	GM_SERIAL_MODE			16 bit r/w	Serial Mode Register */
1802 enum {
1803 	GM_SMOD_DATABL_MSK	= 0x1f<<11, /* Bit 15..11:	Data Blinder (r/o) */
1804 	GM_SMOD_LIMIT_4		= 1<<10, /* 4 consecutive Tx trials */
1805 	GM_SMOD_VLAN_ENA	= 1<<9,	 /* Enable VLAN  (Max. Frame Len) */
1806 	GM_SMOD_JUMBO_ENA	= 1<<8,	 /* Enable Jumbo (Max. Frame Len) */
1807 
1808 	GM_NEW_FLOW_CTRL	= 1<<6,	 /* Enable New Flow-Control */
1809 
1810 	GM_SMOD_IPG_MSK		= 0x1f	 /* Bit 4..0:	Inter-Packet Gap (IPG) */
1811 };
1812 
1813 #define DATA_BLIND_VAL(x)	(((x)<<11) & GM_SMOD_DATABL_MSK)
1814 #define IPG_DATA_VAL(x)		(x & GM_SMOD_IPG_MSK)
1815 
1816 #define DATA_BLIND_DEF		0x04
1817 #define IPG_DATA_DEF_1000	0x1e
1818 #define IPG_DATA_DEF_10_100	0x18
1819 
1820 /*	GM_SMI_CTRL			16 bit r/w	SMI Control Register */
1821 enum {
1822 	GM_SMI_CT_PHY_A_MSK	= 0x1f<<11,/* Bit 15..11:	PHY Device Address */
1823 	GM_SMI_CT_REG_A_MSK	= 0x1f<<6,/* Bit 10.. 6:	PHY Register Address */
1824 	GM_SMI_CT_OP_RD		= 1<<5,	/* Bit  5:	OpCode Read (0=Write)*/
1825 	GM_SMI_CT_RD_VAL	= 1<<4,	/* Bit  4:	Read Valid (Read completed) */
1826 	GM_SMI_CT_BUSY		= 1<<3,	/* Bit  3:	Busy (Operation in progress) */
1827 };
1828 
1829 #define GM_SMI_CT_PHY_AD(x)	(((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
1830 #define GM_SMI_CT_REG_AD(x)	(((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
1831 
1832 /*	GM_PHY_ADDR				16 bit r/w	GPHY Address Register */
1833 enum {
1834 	GM_PAR_MIB_CLR	= 1<<5,	/* Bit  5:	Set MIB Clear Counter Mode */
1835 	GM_PAR_MIB_TST	= 1<<4,	/* Bit  4:	MIB Load Counter (Test Mode) */
1836 };
1837 
1838 /* Receive Frame Status Encoding */
1839 enum {
1840 	GMR_FS_LEN	= 0x7fff<<16, /* Bit 30..16:	Rx Frame Length */
1841 	GMR_FS_VLAN	= 1<<13, /* VLAN Packet */
1842 	GMR_FS_JABBER	= 1<<12, /* Jabber Packet */
1843 	GMR_FS_UN_SIZE	= 1<<11, /* Undersize Packet */
1844 	GMR_FS_MC	= 1<<10, /* Multicast Packet */
1845 	GMR_FS_BC	= 1<<9,  /* Broadcast Packet */
1846 	GMR_FS_RX_OK	= 1<<8,  /* Receive OK (Good Packet) */
1847 	GMR_FS_GOOD_FC	= 1<<7,  /* Good Flow-Control Packet */
1848 	GMR_FS_BAD_FC	= 1<<6,  /* Bad  Flow-Control Packet */
1849 	GMR_FS_MII_ERR	= 1<<5,  /* MII Error */
1850 	GMR_FS_LONG_ERR	= 1<<4,  /* Too Long Packet */
1851 	GMR_FS_FRAGMENT	= 1<<3,  /* Fragment */
1852 
1853 	GMR_FS_CRC_ERR	= 1<<1,  /* CRC Error */
1854 	GMR_FS_RX_FF_OV	= 1<<0,  /* Rx FIFO Overflow */
1855 
1856 	GMR_FS_ANY_ERR	= GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1857 			  GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1858 		  	  GMR_FS_MII_ERR | GMR_FS_BAD_FC |
1859 			  GMR_FS_UN_SIZE | GMR_FS_JABBER,
1860 };
1861 
1862 /*	RX_GMF_CTRL_T	32 bit	Rx GMAC FIFO Control/Test */
1863 enum {
1864 	RX_GCLKMAC_ENA	= 1<<31,	/* RX MAC Clock Gating Enable */
1865 	RX_GCLKMAC_OFF	= 1<<30,
1866 
1867 	RX_STFW_DIS	= 1<<29,	/* RX Store and Forward Enable */
1868 	RX_STFW_ENA	= 1<<28,
1869 
1870 	RX_TRUNC_ON	= 1<<27,  	/* enable  packet truncation */
1871 	RX_TRUNC_OFF	= 1<<26, 	/* disable packet truncation */
1872 	RX_VLAN_STRIP_ON = 1<<25,	/* enable  VLAN stripping */
1873 	RX_VLAN_STRIP_OFF = 1<<24,	/* disable VLAN stripping */
1874 
1875 	RX_MACSEC_FLUSH_ON  = 1<<23,
1876 	RX_MACSEC_FLUSH_OFF = 1<<22,
1877 	RX_MACSEC_ASF_FLUSH_ON = 1<<21,
1878 	RX_MACSEC_ASF_FLUSH_OFF = 1<<20,
1879 
1880 	GMF_RX_OVER_ON      = 1<<19,	/* enable flushing on receive overrun */
1881 	GMF_RX_OVER_OFF     = 1<<18,	/* disable flushing on receive overrun */
1882 	GMF_ASF_RX_OVER_ON  = 1<<17,	/* enable flushing of ASF when overrun */
1883 	GMF_ASF_RX_OVER_OFF = 1<<16,	/* disable flushing of ASF when overrun */
1884 
1885 	GMF_WP_TST_ON	= 1<<14,	/* Write Pointer Test On */
1886 	GMF_WP_TST_OFF	= 1<<13,	/* Write Pointer Test Off */
1887 	GMF_WP_STEP	= 1<<12,	/* Write Pointer Step/Increment */
1888 
1889 	GMF_RP_TST_ON	= 1<<10,	/* Read Pointer Test On */
1890 	GMF_RP_TST_OFF	= 1<<9,		/* Read Pointer Test Off */
1891 	GMF_RP_STEP	= 1<<8,		/* Read Pointer Step/Increment */
1892 	GMF_RX_F_FL_ON	= 1<<7,		/* Rx FIFO Flush Mode On */
1893 	GMF_RX_F_FL_OFF	= 1<<6,		/* Rx FIFO Flush Mode Off */
1894 	GMF_CLI_RX_FO	= 1<<5,		/* Clear IRQ Rx FIFO Overrun */
1895 	GMF_CLI_RX_C	= 1<<4,		/* Clear IRQ Rx Frame Complete */
1896 
1897 	GMF_OPER_ON	= 1<<3,		/* Operational Mode On */
1898 	GMF_OPER_OFF	= 1<<2,		/* Operational Mode Off */
1899 	GMF_RST_CLR	= 1<<1,		/* Clear GMAC FIFO Reset */
1900 	GMF_RST_SET	= 1<<0,		/* Set   GMAC FIFO Reset */
1901 
1902 	RX_GMF_FL_THR_DEF = 0xa,	/* flush threshold (default) */
1903 
1904 	GMF_RX_CTRL_DEF	= GMF_OPER_ON | GMF_RX_F_FL_ON,
1905 };
1906 
1907 /*	RX_GMF_FL_CTRL	16 bit	Rx GMAC FIFO Flush Control (Yukon-Supreme) */
1908 enum {
1909 	RX_IPV6_SA_MOB_ENA	= 1<<9,	/* IPv6 SA Mobility Support Enable */
1910 	RX_IPV6_SA_MOB_DIS	= 1<<8,	/* IPv6 SA Mobility Support Disable */
1911 	RX_IPV6_DA_MOB_ENA	= 1<<7,	/* IPv6 DA Mobility Support Enable */
1912 	RX_IPV6_DA_MOB_DIS	= 1<<6,	/* IPv6 DA Mobility Support Disable */
1913 	RX_PTR_SYNCDLY_ENA	= 1<<5,	/* Pointers Delay Synch Enable */
1914 	RX_PTR_SYNCDLY_DIS	= 1<<4,	/* Pointers Delay Synch Disable */
1915 	RX_ASF_NEWFLAG_ENA	= 1<<3,	/* RX ASF Flag New Logic Enable */
1916 	RX_ASF_NEWFLAG_DIS	= 1<<2,	/* RX ASF Flag New Logic Disable */
1917 	RX_FLSH_MISSPKT_ENA	= 1<<1,	/* RX Flush Miss-Packet Enable */
1918 	RX_FLSH_MISSPKT_DIS	= 1<<0,	/* RX Flush Miss-Packet Disable */
1919 };
1920 
1921 /*	TX_GMF_EA		32 bit	Tx GMAC FIFO End Address */
1922 enum {
1923 	TX_DYN_WM_ENA	= 3,	/* Yukon-FE+ specific */
1924 };
1925 
1926 /*	TX_GMF_CTRL_T	32 bit	Tx GMAC FIFO Control/Test */
1927 enum {
1928 	TX_STFW_DIS	= 1<<31,/* Disable Store & Forward */
1929 	TX_STFW_ENA	= 1<<30,/* Enable  Store & Forward */
1930 
1931 	TX_VLAN_TAG_ON	= 1<<25,/* enable  VLAN tagging */
1932 	TX_VLAN_TAG_OFF	= 1<<24,/* disable VLAN tagging */
1933 
1934 	TX_PCI_JUM_ENA  = 1<<23,/* PCI Jumbo Mode enable */
1935 	TX_PCI_JUM_DIS  = 1<<22,/* PCI Jumbo Mode enable */
1936 
1937 	GMF_WSP_TST_ON	= 1<<18,/* Write Shadow Pointer Test On */
1938 	GMF_WSP_TST_OFF	= 1<<17,/* Write Shadow Pointer Test Off */
1939 	GMF_WSP_STEP	= 1<<16,/* Write Shadow Pointer Step/Increment */
1940 
1941 	GMF_CLI_TX_FU	= 1<<6,	/* Clear IRQ Tx FIFO Underrun */
1942 	GMF_CLI_TX_FC	= 1<<5,	/* Clear IRQ Tx Frame Complete */
1943 	GMF_CLI_TX_PE	= 1<<4,	/* Clear IRQ Tx Parity Error */
1944 };
1945 
1946 /*	GMAC_TI_ST_CTRL	 8 bit	Time Stamp Timer Ctrl Reg (YUKON only) */
1947 enum {
1948 	GMT_ST_START	= 1<<2,	/* Start Time Stamp Timer */
1949 	GMT_ST_STOP	= 1<<1,	/* Stop  Time Stamp Timer */
1950 	GMT_ST_CLR_IRQ	= 1<<0,	/* Clear Time Stamp Timer IRQ */
1951 };
1952 
1953 /* B28_Y2_ASF_STAT_CMD		32 bit	ASF Status and Command Reg */
1954 enum {
1955 	Y2_ASF_OS_PRES	= 1<<4,	/* ASF operation system present */
1956 	Y2_ASF_RESET	= 1<<3,	/* ASF system in reset state */
1957 	Y2_ASF_RUNNING	= 1<<2,	/* ASF system operational */
1958 	Y2_ASF_CLR_HSTI = 1<<1,	/* Clear ASF IRQ */
1959 	Y2_ASF_IRQ	= 1<<0,	/* Issue an IRQ to ASF system */
1960 
1961 	Y2_ASF_UC_STATE = 3<<2,	/* ASF uC State */
1962 	Y2_ASF_CLK_HALT	= 0,	/* ASF system clock stopped */
1963 };
1964 
1965 /* B28_Y2_ASF_HOST_COM	32 bit	ASF Host Communication Reg */
1966 enum {
1967 	Y2_ASF_CLR_ASFI = 1<<1,	/* Clear host IRQ */
1968 	Y2_ASF_HOST_IRQ = 1<<0,	/* Issue an IRQ to HOST system */
1969 };
1970 /*	HCU_CCSR	CPU Control and Status Register */
1971 enum {
1972 	HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
1973 	HCU_CCSR_CPU_SLEEP	= 1<<26, /* CPU sleep status */
1974 	/* Clock Stretching Timeout */
1975 	HCU_CCSR_CS_TO		= 1<<25,
1976 	HCU_CCSR_WDOG		= 1<<24, /* Watchdog Reset */
1977 
1978 	HCU_CCSR_CLR_IRQ_HOST	= 1<<17, /* Clear IRQ_HOST */
1979 	HCU_CCSR_SET_IRQ_HCU	= 1<<16, /* Set IRQ_HCU */
1980 
1981 	HCU_CCSR_AHB_RST	= 1<<9, /* Reset AHB bridge */
1982 	HCU_CCSR_CPU_RST_MODE	= 1<<8, /* CPU Reset Mode */
1983 
1984 	HCU_CCSR_SET_SYNC_CPU	= 1<<5,
1985 	HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
1986 	HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
1987 	HCU_CCSR_OS_PRSNT	= 1<<2, /* ASF OS Present */
1988 /* Microcontroller State */
1989 	HCU_CCSR_UC_STATE_MSK	= 3,
1990 	HCU_CCSR_UC_STATE_BASE	= 1<<0,
1991 	HCU_CCSR_ASF_RESET	= 0,
1992 	HCU_CCSR_ASF_HALTED	= 1<<1,
1993 	HCU_CCSR_ASF_RUNNING	= 1<<0,
1994 };
1995 
1996 /*	HCU_HCSR	Host Control and Status Register */
1997 enum {
1998 	HCU_HCSR_SET_IRQ_CPU	= 1<<16, /* Set IRQ_CPU */
1999 
2000 	HCU_HCSR_CLR_IRQ_HCU	= 1<<1, /* Clear IRQ_HCU */
2001 	HCU_HCSR_SET_IRQ_HOST	= 1<<0,	/* Set IRQ_HOST */
2002 };
2003 
2004 /*	STAT_CTRL		32 bit	Status BMU control register (Yukon-2 only) */
2005 enum {
2006 	SC_STAT_CLR_IRQ	= 1<<4,	/* Status Burst IRQ clear */
2007 	SC_STAT_OP_ON	= 1<<3,	/* Operational Mode On */
2008 	SC_STAT_OP_OFF	= 1<<2,	/* Operational Mode Off */
2009 	SC_STAT_RST_CLR	= 1<<1,	/* Clear Status Unit Reset (Enable) */
2010 	SC_STAT_RST_SET	= 1<<0,	/* Set   Status Unit Reset */
2011 };
2012 
2013 /*	GMAC_CTRL		32 bit	GMAC Control Reg (YUKON only) */
2014 enum {
2015 	GMC_SET_RST	    = 1<<15,/* MAC SEC RST */
2016 	GMC_SEC_RST_OFF     = 1<<14,/* MAC SEC RSt OFF */
2017 	GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */
2018 	GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */
2019 	GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */
2020 	GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX  off*/
2021 	GMC_BYP_RETR_ON	= 1<<9, /* Bypass retransmit FIFO On */
2022 	GMC_BYP_RETR_OFF= 1<<8, /* Bypass retransmit FIFO Off */
2023 
2024 	GMC_H_BURST_ON	= 1<<7,	/* Half Duplex Burst Mode On */
2025 	GMC_H_BURST_OFF	= 1<<6,	/* Half Duplex Burst Mode Off */
2026 	GMC_F_LOOPB_ON	= 1<<5,	/* FIFO Loopback On */
2027 	GMC_F_LOOPB_OFF	= 1<<4,	/* FIFO Loopback Off */
2028 	GMC_PAUSE_ON	= 1<<3,	/* Pause On */
2029 	GMC_PAUSE_OFF	= 1<<2,	/* Pause Off */
2030 	GMC_RST_CLR	= 1<<1,	/* Clear GMAC Reset */
2031 	GMC_RST_SET	= 1<<0,	/* Set   GMAC Reset */
2032 };
2033 
2034 /*	GPHY_CTRL		32 bit	GPHY Control Reg (YUKON only) */
2035 enum {
2036 	GPC_TX_PAUSE	= 1<<30, /* Tx pause enabled (ro) */
2037 	GPC_RX_PAUSE	= 1<<29, /* Rx pause enabled (ro) */
2038 	GPC_SPEED	= 3<<27, /* PHY speed (ro) */
2039 	GPC_LINK	= 1<<26, /* Link up (ro) */
2040 	GPC_DUPLEX	= 1<<25, /* Duplex (ro) */
2041 	GPC_CLOCK	= 1<<24, /* 125Mhz clock stable (ro) */
2042 
2043 	GPC_PDOWN	= 1<<23, /* Internal regulator 2.5 power down */
2044 	GPC_TSTMODE	= 1<<22, /* Test mode */
2045 	GPC_REG18	= 1<<21, /* Reg18 Power down */
2046 	GPC_REG12SEL	= 3<<19, /* Reg12 power setting */
2047 	GPC_REG18SEL	= 3<<17, /* Reg18 power setting */
2048 	GPC_SPILOCK	= 1<<16, /* SPI lock (ASF) */
2049 
2050 	GPC_LEDMUX	= 3<<14, /* LED Mux */
2051 	GPC_INTPOL	= 1<<13, /* Interrupt polarity */
2052 	GPC_DETECT	= 1<<12, /* Energy detect */
2053 	GPC_1000HD	= 1<<11, /* Enable 1000Mbit HD */
2054 	GPC_SLAVE	= 1<<10, /* Slave mode */
2055 	GPC_PAUSE	= 1<<9, /* Pause enable */
2056 	GPC_LEDCTL	= 3<<6, /* GPHY Leds */
2057 
2058 	GPC_RST_CLR	= 1<<1,	/* Clear GPHY Reset */
2059 	GPC_RST_SET	= 1<<0,	/* Set   GPHY Reset */
2060 };
2061 
2062 /*	GMAC_IRQ_SRC	 8 bit	GMAC Interrupt Source Reg (YUKON only) */
2063 /*	GMAC_IRQ_MSK	 8 bit	GMAC Interrupt Mask   Reg (YUKON only) */
2064 enum {
2065 	GM_IS_TX_CO_OV	= 1<<5,	/* Transmit Counter Overflow IRQ */
2066 	GM_IS_RX_CO_OV	= 1<<4,	/* Receive Counter Overflow IRQ */
2067 	GM_IS_TX_FF_UR	= 1<<3,	/* Transmit FIFO Underrun */
2068 	GM_IS_TX_COMPL	= 1<<2,	/* Frame Transmission Complete */
2069 	GM_IS_RX_FF_OR	= 1<<1,	/* Receive FIFO Overrun */
2070 	GM_IS_RX_COMPL	= 1<<0,	/* Frame Reception Complete */
2071 
2072 #define GMAC_DEF_MSK     (GM_IS_TX_FF_UR | GM_IS_RX_FF_OR)
2073 };
2074 
2075 /*	GMAC_LINK_CTRL	16 bit	GMAC Link Control Reg (YUKON only) */
2076 enum {						/* Bits 15.. 2:	reserved */
2077 	GMLC_RST_CLR	= 1<<1,	/* Clear GMAC Link Reset */
2078 	GMLC_RST_SET	= 1<<0,	/* Set   GMAC Link Reset */
2079 };
2080 
2081 
2082 /*	WOL_CTRL_STAT	16 bit	WOL Control/Status Reg */
2083 enum {
2084 	WOL_CTL_LINK_CHG_OCC		= 1<<15,
2085 	WOL_CTL_MAGIC_PKT_OCC		= 1<<14,
2086 	WOL_CTL_PATTERN_OCC		= 1<<13,
2087 	WOL_CTL_CLEAR_RESULT		= 1<<12,
2088 	WOL_CTL_ENA_PME_ON_LINK_CHG	= 1<<11,
2089 	WOL_CTL_DIS_PME_ON_LINK_CHG	= 1<<10,
2090 	WOL_CTL_ENA_PME_ON_MAGIC_PKT	= 1<<9,
2091 	WOL_CTL_DIS_PME_ON_MAGIC_PKT	= 1<<8,
2092 	WOL_CTL_ENA_PME_ON_PATTERN	= 1<<7,
2093 	WOL_CTL_DIS_PME_ON_PATTERN	= 1<<6,
2094 	WOL_CTL_ENA_LINK_CHG_UNIT	= 1<<5,
2095 	WOL_CTL_DIS_LINK_CHG_UNIT	= 1<<4,
2096 	WOL_CTL_ENA_MAGIC_PKT_UNIT	= 1<<3,
2097 	WOL_CTL_DIS_MAGIC_PKT_UNIT	= 1<<2,
2098 	WOL_CTL_ENA_PATTERN_UNIT	= 1<<1,
2099 	WOL_CTL_DIS_PATTERN_UNIT	= 1<<0,
2100 };
2101 
2102 
2103 /* Control flags */
2104 enum {
2105 	UDPTCP	= 1<<0,
2106 	CALSUM	= 1<<1,
2107 	WR_SUM	= 1<<2,
2108 	INIT_SUM= 1<<3,
2109 	LOCK_SUM= 1<<4,
2110 	INS_VLAN= 1<<5,
2111 	EOP	= 1<<7,
2112 };
2113 
2114 enum {
2115 	HW_OWNER 	= 1<<7,
2116 	OP_TCPWRITE	= 0x11,
2117 	OP_TCPSTART	= 0x12,
2118 	OP_TCPINIT	= 0x14,
2119 	OP_TCPLCK	= 0x18,
2120 	OP_TCPCHKSUM	= OP_TCPSTART,
2121 	OP_TCPIS	= OP_TCPINIT | OP_TCPSTART,
2122 	OP_TCPLW	= OP_TCPLCK | OP_TCPWRITE,
2123 	OP_TCPLSW	= OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
2124 	OP_TCPLISW	= OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
2125 
2126 	OP_ADDR64	= 0x21,
2127 	OP_VLAN		= 0x22,
2128 	OP_ADDR64VLAN	= OP_ADDR64 | OP_VLAN,
2129 	OP_LRGLEN	= 0x24,
2130 	OP_LRGLENVLAN	= OP_LRGLEN | OP_VLAN,
2131 	OP_MSS		= 0x28,
2132 	OP_MSSVLAN	= OP_MSS | OP_VLAN,
2133 
2134 	OP_BUFFER	= 0x40,
2135 	OP_PACKET	= 0x41,
2136 	OP_LARGESEND	= 0x43,
2137 	OP_LSOV2	= 0x45,
2138 
2139 /* YUKON-2 STATUS opcodes defines */
2140 	OP_RXSTAT	= 0x60,
2141 	OP_RXTIMESTAMP	= 0x61,
2142 	OP_RXVLAN	= 0x62,
2143 	OP_RXCHKS	= 0x64,
2144 	OP_RXCHKSVLAN	= OP_RXCHKS | OP_RXVLAN,
2145 	OP_RXTIMEVLAN	= OP_RXTIMESTAMP | OP_RXVLAN,
2146 	OP_RSS_HASH	= 0x65,
2147 	OP_TXINDEXLE	= 0x68,
2148 	OP_MACSEC	= 0x6c,
2149 	OP_PUTIDX	= 0x70,
2150 };
2151 
2152 enum status_css {
2153 	CSS_TCPUDPCSOK	= 1<<7,	/* TCP / UDP checksum is ok */
2154 	CSS_ISUDP	= 1<<6, /* packet is a UDP packet */
2155 	CSS_ISTCP	= 1<<5, /* packet is a TCP packet */
2156 	CSS_ISIPFRAG	= 1<<4, /* packet is a TCP/UDP frag, CS calc not done */
2157 	CSS_ISIPV6	= 1<<3, /* packet is a IPv6 packet */
2158 	CSS_IPV4CSUMOK	= 1<<2, /* IP v4: TCP header checksum is ok */
2159 	CSS_ISIPV4	= 1<<1, /* packet is a IPv4 packet */
2160 	CSS_LINK_BIT	= 1<<0, /* port number (legacy) */
2161 };
2162 
2163 /* Yukon 2 hardware interface */
2164 struct sky2_tx_le {
2165 	__le32	addr;
2166 	__le16	length;	/* also vlan tag or checksum start */
2167 	u8	ctrl;
2168 	u8	opcode;
2169 } __packed;
2170 
2171 struct sky2_rx_le {
2172 	__le32	addr;
2173 	__le16	length;
2174 	u8	ctrl;
2175 	u8	opcode;
2176 } __packed;
2177 
2178 struct sky2_status_le {
2179 	__le32	status;	/* also checksum */
2180 	__le16	length;	/* also vlan tag */
2181 	u8	css;
2182 	u8	opcode;
2183 } __packed;
2184 
2185 struct tx_ring_info {
2186 	struct sk_buff	*skb;
2187 	unsigned long flags;
2188 #define TX_MAP_SINGLE   0x0001
2189 #define TX_MAP_PAGE     0x0002
2190 	DEFINE_DMA_UNMAP_ADDR(mapaddr);
2191 	DEFINE_DMA_UNMAP_LEN(maplen);
2192 };
2193 
2194 struct rx_ring_info {
2195 	struct sk_buff	*skb;
2196 	dma_addr_t	data_addr;
2197 	DEFINE_DMA_UNMAP_LEN(data_size);
2198 	dma_addr_t	frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT ?: 1];
2199 };
2200 
2201 enum flow_control {
2202 	FC_NONE	= 0,
2203 	FC_TX	= 1,
2204 	FC_RX	= 2,
2205 	FC_BOTH	= 3,
2206 };
2207 
2208 struct sky2_stats {
2209 	struct u64_stats_sync syncp;
2210 	u64		packets;
2211 	u64		bytes;
2212 };
2213 
2214 struct sky2_port {
2215 	struct sky2_hw	     *hw;
2216 	struct net_device    *netdev;
2217 	unsigned	     port;
2218 	u32		     msg_enable;
2219 	spinlock_t	     phy_lock;
2220 
2221 	struct tx_ring_info  *tx_ring;
2222 	struct sky2_tx_le    *tx_le;
2223 	struct sky2_stats    tx_stats;
2224 
2225 	u16		     tx_ring_size;
2226 	u16		     tx_cons;		/* next le to check */
2227 	u16		     tx_prod;		/* next le to use */
2228 	u16		     tx_next;		/* debug only */
2229 
2230 	u16		     tx_pending;
2231 	u16		     tx_last_mss;
2232 	u32		     tx_last_upper;
2233 	u32		     tx_tcpsum;
2234 
2235 	struct rx_ring_info  *rx_ring ____cacheline_aligned_in_smp;
2236 	struct sky2_rx_le    *rx_le;
2237 	struct sky2_stats    rx_stats;
2238 
2239 	u16		     rx_next;		/* next re to check */
2240 	u16		     rx_put;		/* next le index to use */
2241 	u16		     rx_pending;
2242 	u16		     rx_data_size;
2243 	u16		     rx_nfrags;
2244 
2245 	unsigned long	     last_rx;
2246 	struct {
2247 		unsigned long last;
2248 		u32	mac_rp;
2249 		u8	mac_lev;
2250 		u8	fifo_rp;
2251 		u8	fifo_lev;
2252 	} check;
2253 
2254 	dma_addr_t	     rx_le_map;
2255 	dma_addr_t	     tx_le_map;
2256 
2257 	u16		     advertising;	/* ADVERTISED_ bits */
2258 	u16		     speed;		/* SPEED_1000, SPEED_100, ... */
2259 	u8		     wol;		/* WAKE_ bits */
2260 	u8		     duplex;		/* DUPLEX_HALF, DUPLEX_FULL */
2261 	u16		     flags;
2262 #define SKY2_FLAG_AUTO_SPEED		0x0002
2263 #define SKY2_FLAG_AUTO_PAUSE		0x0004
2264 
2265  	enum flow_control    flow_mode;
2266  	enum flow_control    flow_status;
2267 
2268 #ifdef CONFIG_SKY2_DEBUG
2269 	struct dentry	     *debugfs;
2270 #endif
2271 };
2272 
2273 struct sky2_hw {
2274 	void __iomem  	     *regs;
2275 	struct pci_dev	     *pdev;
2276 	struct napi_struct   napi;
2277 	struct net_device    *dev[2];
2278 	unsigned long	     flags;
2279 #define SKY2_HW_USE_MSI		0x00000001
2280 #define SKY2_HW_FIBRE_PHY	0x00000002
2281 #define SKY2_HW_GIGABIT		0x00000004
2282 #define SKY2_HW_NEWER_PHY	0x00000008
2283 #define SKY2_HW_RAM_BUFFER	0x00000010
2284 #define SKY2_HW_NEW_LE		0x00000020	/* new LSOv2 format */
2285 #define SKY2_HW_AUTO_TX_SUM	0x00000040	/* new IP decode for Tx */
2286 #define SKY2_HW_ADV_POWER_CTL	0x00000080	/* additional PHY power regs */
2287 #define SKY2_HW_RSS_BROKEN	0x00000100
2288 #define SKY2_HW_VLAN_BROKEN     0x00000200
2289 #define SKY2_HW_RSS_CHKSUM	0x00000400	/* RSS requires chksum */
2290 #define SKY2_HW_IRQ_SETUP	0x00000800
2291 
2292 	u8	     	     chip_id;
2293 	u8		     chip_rev;
2294 	u8		     pmd_type;
2295 	u8		     ports;
2296 
2297 	struct sky2_status_le *st_le;
2298 	u32		     st_size;
2299 	u32		     st_idx;
2300 	dma_addr_t   	     st_dma;
2301 
2302 	struct timer_list    watchdog_timer;
2303 	struct work_struct   restart_work;
2304 	wait_queue_head_t    msi_wait;
2305 
2306 	char		     irq_name[];
2307 };
2308 
sky2_is_copper(const struct sky2_hw * hw)2309 static inline int sky2_is_copper(const struct sky2_hw *hw)
2310 {
2311 	return !(hw->flags & SKY2_HW_FIBRE_PHY);
2312 }
2313 
2314 /* Register accessor for memory mapped device */
sky2_read32(const struct sky2_hw * hw,unsigned reg)2315 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
2316 {
2317 	return readl(hw->regs + reg);
2318 }
2319 
sky2_read16(const struct sky2_hw * hw,unsigned reg)2320 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
2321 {
2322 	return readw(hw->regs + reg);
2323 }
2324 
sky2_read8(const struct sky2_hw * hw,unsigned reg)2325 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
2326 {
2327 	return readb(hw->regs + reg);
2328 }
2329 
sky2_write32(const struct sky2_hw * hw,unsigned reg,u32 val)2330 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
2331 {
2332 	writel(val, hw->regs + reg);
2333 }
2334 
sky2_write16(const struct sky2_hw * hw,unsigned reg,u16 val)2335 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
2336 {
2337 	writew(val, hw->regs + reg);
2338 }
2339 
sky2_write8(const struct sky2_hw * hw,unsigned reg,u8 val)2340 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
2341 {
2342 	writeb(val, hw->regs + reg);
2343 }
2344 
2345 /* Yukon PHY related registers */
2346 #define SK_GMAC_REG(port,reg) \
2347 	(BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2348 #define GM_PHY_RETRIES	100
2349 
gma_read16(const struct sky2_hw * hw,unsigned port,unsigned reg)2350 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
2351 {
2352 	return sky2_read16(hw, SK_GMAC_REG(port,reg));
2353 }
2354 
gma_read32(struct sky2_hw * hw,unsigned port,unsigned reg)2355 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
2356 {
2357 	unsigned base = SK_GMAC_REG(port, reg);
2358 	return (u32) sky2_read16(hw, base)
2359 		| (u32) sky2_read16(hw, base+4) << 16;
2360 }
2361 
gma_read64(struct sky2_hw * hw,unsigned port,unsigned reg)2362 static inline u64 gma_read64(struct sky2_hw *hw, unsigned port, unsigned reg)
2363 {
2364 	unsigned base = SK_GMAC_REG(port, reg);
2365 
2366 	return (u64) sky2_read16(hw, base)
2367 		| (u64) sky2_read16(hw, base+4) << 16
2368 		| (u64) sky2_read16(hw, base+8) << 32
2369 		| (u64) sky2_read16(hw, base+12) << 48;
2370 }
2371 
2372 /* There is no way to atomically read32 bit values from PHY, so retry */
get_stats32(struct sky2_hw * hw,unsigned port,unsigned reg)2373 static inline u32 get_stats32(struct sky2_hw *hw, unsigned port, unsigned reg)
2374 {
2375 	u32 val;
2376 
2377 	do {
2378 		val = gma_read32(hw, port, reg);
2379 	} while (gma_read32(hw, port, reg) != val);
2380 
2381 	return val;
2382 }
2383 
get_stats64(struct sky2_hw * hw,unsigned port,unsigned reg)2384 static inline u64 get_stats64(struct sky2_hw *hw, unsigned port, unsigned reg)
2385 {
2386 	u64 val;
2387 
2388 	do {
2389 		val = gma_read64(hw, port, reg);
2390 	} while (gma_read64(hw, port, reg) != val);
2391 
2392 	return val;
2393 }
2394 
gma_write16(const struct sky2_hw * hw,unsigned port,int r,u16 v)2395 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
2396 {
2397 	sky2_write16(hw, SK_GMAC_REG(port,r), v);
2398 }
2399 
gma_set_addr(struct sky2_hw * hw,unsigned port,unsigned reg,const u8 * addr)2400 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
2401 				    const u8 *addr)
2402 {
2403 	gma_write16(hw, port, reg,  (u16) addr[0] | ((u16) addr[1] << 8));
2404 	gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2405 	gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2406 }
2407 
2408 /* PCI config space access */
sky2_pci_read32(const struct sky2_hw * hw,unsigned reg)2409 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
2410 {
2411 	return sky2_read32(hw, Y2_CFG_SPC + reg);
2412 }
2413 
sky2_pci_read16(const struct sky2_hw * hw,unsigned reg)2414 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
2415 {
2416 	return sky2_read16(hw, Y2_CFG_SPC + reg);
2417 }
2418 
sky2_pci_write32(struct sky2_hw * hw,unsigned reg,u32 val)2419 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
2420 {
2421 	sky2_write32(hw, Y2_CFG_SPC + reg, val);
2422 }
2423 
sky2_pci_write16(struct sky2_hw * hw,unsigned reg,u16 val)2424 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
2425 {
2426 	sky2_write16(hw, Y2_CFG_SPC + reg, val);
2427 }
2428 #endif
2429