/drivers/crypto/ccree/ |
D | cc_aead.h | 51 u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned; 52 u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned; 55 u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned; 56 u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned; 57 u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned; 59 u8 len_a[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned; 63 u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned; 65 unsigned int hw_iv_size ____cacheline_aligned; member
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D | cc_hash.h | 38 u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned; 39 u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; 40 u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; 41 u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; 42 u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned; 43 struct async_gen_req_ctx gen_ctx ____cacheline_aligned; member
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/drivers/target/ |
D | target_core_pscsi.h | 28 } ____cacheline_aligned; variable 47 } ____cacheline_aligned; variable 58 } ____cacheline_aligned; variable
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D | target_core_rd.h | 27 } ____cacheline_aligned; variable 49 } ____cacheline_aligned; variable 54 } ____cacheline_aligned; variable
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D | target_core_iblock.h | 16 } ____cacheline_aligned; variable 27 } ____cacheline_aligned; variable
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D | target_core_file.h | 44 } ____cacheline_aligned; variable 50 } ____cacheline_aligned; variable
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/drivers/scsi/snic/ |
D | snic.h | 306 ____cacheline_aligned spinlock_t io_req_lock[SNIC_IO_LOCKS]; 309 ____cacheline_aligned spinlock_t spl_cmd_lock; 341 ____cacheline_aligned struct vnic_cq cq[SNIC_CQ_MAX]; 344 ____cacheline_aligned struct vnic_wq wq[SNIC_WQ_MAX]; 348 ____cacheline_aligned struct vnic_intr intr[SNIC_MSIX_INTR_MAX]; 367 struct snic_trc trc ____cacheline_aligned; member
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/drivers/net/ethernet/brocade/bna/ |
D | bnad.h | 206 } ____cacheline_aligned; variable 214 } ____cacheline_aligned; variable 254 struct bnad_rx_unmap unmap[] ____cacheline_aligned; 304 struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned; 305 struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned; 322 spinlock_t bna_lock ____cacheline_aligned; member
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/drivers/crypto/ |
D | talitos.h | 96 atomic_t submit_count ____cacheline_aligned; member 99 spinlock_t head_lock ____cacheline_aligned; member 104 spinlock_t tail_lock ____cacheline_aligned; member 124 spinlock_t reg_lock ____cacheline_aligned; member 145 atomic_t last_chan ____cacheline_aligned; member
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D | atmel-i2c.h | 117 } ____cacheline_aligned; variable 141 atomic_t tfm_count ____cacheline_aligned; member
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/drivers/crypto/ccp/ |
D | ccp-dev.h | 273 struct mutex q_mutex ____cacheline_aligned; member 337 } ____cacheline_aligned; variable 364 struct mutex req_mutex ____cacheline_aligned; member 372 spinlock_t cmd_lock ____cacheline_aligned; member 398 atomic_t current_id ____cacheline_aligned; member 417 struct mutex sb_mutex ____cacheline_aligned; member
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/drivers/scsi/fnic/ |
D | fnic.h | 300 ____cacheline_aligned struct vnic_wq_copy wq_copy[FNIC_WQ_COPY_MAX]; 302 ____cacheline_aligned struct vnic_cq cq[FNIC_CQ_MAX]; 307 ____cacheline_aligned struct vnic_wq wq[FNIC_WQ_MAX]; 311 ____cacheline_aligned struct vnic_rq rq[FNIC_RQ_MAX]; 314 ____cacheline_aligned struct vnic_intr intr[FNIC_MSIX_INTR_MAX];
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/drivers/net/ethernet/cisco/enic/ |
D | enic.h | 176 ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX]; 183 ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX]; 191 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; 196 ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
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/drivers/crypto/caam/ |
D | qi.h | 70 } ____cacheline_aligned; variable 91 } ____cacheline_aligned; variable
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D | intern.h | 53 atomic_t tfm_count ____cacheline_aligned; member 57 spinlock_t inplock ____cacheline_aligned; /* Input ring index lock */ member
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/drivers/net/ethernet/google/gve/ |
D | gve.h | 135 __be32 last_nic_done ____cacheline_aligned; /* NIC tail pointer */ member 140 union gve_tx_desc *desc ____cacheline_aligned; member 147 u32 q_num ____cacheline_aligned; /* queue idx */ member 156 } ____cacheline_aligned; variable 168 } ____cacheline_aligned; variable
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/drivers/macintosh/ |
D | rack-meter.c | 44 struct dbdma_cmd cmd[4] ____cacheline_aligned; 45 u32 mark ____cacheline_aligned; member 46 u32 buf1[SAMPLE_COUNT] ____cacheline_aligned; 47 u32 buf2[SAMPLE_COUNT] ____cacheline_aligned; 48 } ____cacheline_aligned; variable 56 } ____cacheline_aligned; variable
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/drivers/target/iscsi/ |
D | iscsi_target_seq_pdu_list.h | 64 } ____cacheline_aligned; variable 83 } ____cacheline_aligned; variable
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D | iscsi_target_auth.h | 43 } ____cacheline_aligned; variable
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/drivers/net/ethernet/amazon/ena/ |
D | ena_netdev.h | 138 struct napi_struct napi ____cacheline_aligned; member 196 } ____cacheline_aligned; variable 203 } ____cacheline_aligned; variable 301 } ____cacheline_aligned; variable
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/drivers/infiniband/hw/ocrdma/ |
D | ocrdma.h | 243 spinlock_t flush_q_lock ____cacheline_aligned; member 325 spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization member 329 spinlock_t comp_handler_lock ____cacheline_aligned; member 382 spinlock_t q_lock ____cacheline_aligned; member 403 spinlock_t q_lock ____cacheline_aligned; member
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/drivers/net/ethernet/neterion/vxge/ |
D | vxge-config.h | 636 u32 post_index ____cacheline_aligned; member 637 u32 compl_index ____cacheline_aligned; member 647 } ____cacheline_aligned; variable 696 struct __vxge_hw_ring *____cacheline_aligned ringh; 697 struct __vxge_hw_fifo *____cacheline_aligned fifoh; 953 struct vxge_hw_vpath_stats_sw_ring_info *stats ____cacheline_aligned; member 955 } ____cacheline_aligned; variable 1034 struct vxge_hw_vpath_stats_sw_fifo_info *stats ____cacheline_aligned; member 1035 } ____cacheline_aligned; variable
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/drivers/soc/fsl/qbman/ |
D | bman_test_api.c | 38 static struct bm_buffer bufs_in[NUM_BUFS] ____cacheline_aligned; 39 static struct bm_buffer bufs_out[NUM_BUFS] ____cacheline_aligned;
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/drivers/net/wireless/realtek/rtl818x/rtl8187/ |
D | rtl8187.h | 144 } ____cacheline_aligned; member 153 } *io_dmabuf ____cacheline_aligned; member
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/drivers/iio/adc/ |
D | ti-adc108s102.c | 80 __be16 rx_buf[13] ____cacheline_aligned; 81 __be16 tx_buf[9] ____cacheline_aligned;
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