| /drivers/clk/sunxi-ng/ |
| D | ccu_gate.h | 19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
21 .enable = _gate, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
33 .enable = _gate, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
45 .enable = _gate, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
61 .enable = _gate, \
71 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
73 .enable = _gate, \
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| D | ccu_nm.h | 43 _gate, _lock, _flags) \ argument
45 .enable = _gate, \
66 _gate, _lock, _flags) \ argument
68 .enable = _gate, \
91 _gate, _lock, _flags) \ argument
93 .enable = _gate, \
119 _gate, _lock, _flags) \ argument
121 .enable = _gate, \
143 _gate, _lock, _flags) \ argument
145 .enable = _gate, \
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| D | ccu_div.h | 89 _table, _gate, _flags) \ argument
93 .enable = _gate, \
116 _gate, _flags) \ argument
118 .enable = _gate, \
132 _gate, _flags) \ argument
137 _gate, _flags)
150 _mshift, _mwidth, _gate, \ argument
153 .enable = _gate, \
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| D | ccu_nkm.h | 39 _gate, _lock, _flags) \ argument
41 .enable = _gate, \
60 _gate, _lock, _flags) \ argument
62 .enable = _gate, \
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| D | ccu_mp.h | 38 _gate, _postdiv, _flags) \ argument
40 .enable = _gate, \
59 _gate, _flags) \ argument
61 .enable = _gate, \
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| D | ccu_mux.h | 51 _reg, _shift, _width, _gate, \ argument
54 .enable = _gate, \
66 _shift, _width, _gate, _flags) \ argument
68 _reg, _shift, _width, _gate, \
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| D | ccu_nk.h | 36 _gate, _lock, _postdiv, \ argument
39 .enable = _gate, \
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| D | ccu_nkmp.h | 40 _gate, _lock, _flags) \ argument
42 .enable = _gate, \
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| D | ccu_mult.h | 46 _mshift, _mwidth, _gate, _lock, \ argument
49 .enable = _gate, \
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| /drivers/clk/actions/ |
| D | owl-composite.h | 38 _mux, _gate, _div, _flags) \ argument
41 .gate_hw = _gate, \
53 _gate, _div, _flags) \ argument
55 .gate_hw = _gate, \
67 _mux, _gate, _factor, _flags) \ argument
70 .gate_hw = _gate, \
82 _gate, _mul, _div, _flags) \ argument
84 .gate_hw = _gate, \
98 _mux, _gate, _flags) \ argument
101 .gate_hw = _gate, \
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| /drivers/clk/mediatek/ |
| D | clk-mux.h | 47 _gate, _upd_ofs, _upd, _flags, _ops) { \ argument
56 .gate_shift = _gate, \
66 _gate, _upd_ofs, _upd, _flags) \ argument
69 _gate, _upd_ofs, _upd, _flags, \
74 _gate, _upd_ofs, _upd) \ argument
77 _width, _gate, _upd_ofs, _upd, \
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| D | clk-mtk.h | 82 _width, _gate, _flags, _muxflags) { \ argument
89 .gate_shift = _gate, \
102 _gate, _flags) \ argument
104 _shift, _width, _gate, _flags, 0)
110 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
112 _gate, CLK_SET_RATE_PARENT)
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| /drivers/clk/ |
| D | clk-stm32mp1.c | 663 #define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate) argument
1186 #define STM32_GATE(_id, _name, _parent, _flags, _gate)\ argument
1192 .cfg = (struct stm32_gate_cfg *) {_gate},\
1270 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\ argument
1278 _gate,\
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| D | clk-stm32f4.c | 521 #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate) argument
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| /drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 1206 #define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate) \ argument
1215 .gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\
1216 &clk_hw_proto[CLK_PREFIX(_gate)].hw0), \
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