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Searched refs:bw (Results 1 – 25 of 248) sorted by relevance

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/drivers/net/wireless/ath/ath11k/
Dreg.c457 u16 bw; in ath11k_reg_adjust_bw() local
462 bw = end_freq - start_freq; in ath11k_reg_adjust_bw()
463 bw = min_t(u16, bw, max_bw); in ath11k_reg_adjust_bw()
465 if (bw >= 80 && bw < 160) in ath11k_reg_adjust_bw()
466 bw = 80; in ath11k_reg_adjust_bw()
467 else if (bw >= 40 && bw < 80) in ath11k_reg_adjust_bw()
468 bw = 40; in ath11k_reg_adjust_bw()
469 else if (bw >= 20 && bw < 40) in ath11k_reg_adjust_bw()
470 bw = 20; in ath11k_reg_adjust_bw()
472 bw = 0; in ath11k_reg_adjust_bw()
[all …]
Ddebugfs_sta.c21 int gi, mcs, bw, nss; in ath11k_debugfs_sta_add_tx_stats() local
29 bw = ath11k_mac_mac80211_bw_to_ath11k_bw(txrate->bw); in ath11k_debugfs_sta_add_tx_stats()
85 STATS_OP_FMT(AMPDU).bw[0][bw] += in ath11k_debugfs_sta_add_tx_stats()
91 STATS_OP_FMT(AMPDU).bw[1][bw] += in ath11k_debugfs_sta_add_tx_stats()
101 STATS_OP_FMT(SUCC).bw[0][bw] += peer_stats->succ_bytes; in ath11k_debugfs_sta_add_tx_stats()
105 STATS_OP_FMT(SUCC).bw[1][bw] += peer_stats->succ_pkts; in ath11k_debugfs_sta_add_tx_stats()
109 STATS_OP_FMT(FAIL).bw[0][bw] += peer_stats->failed_bytes; in ath11k_debugfs_sta_add_tx_stats()
113 STATS_OP_FMT(FAIL).bw[1][bw] += peer_stats->failed_pkts; in ath11k_debugfs_sta_add_tx_stats()
117 STATS_OP_FMT(RETRY).bw[0][bw] += peer_stats->retry_bytes; in ath11k_debugfs_sta_add_tx_stats()
121 STATS_OP_FMT(RETRY).bw[1][bw] += peer_stats->retry_pkts; in ath11k_debugfs_sta_add_tx_stats()
[all …]
/drivers/net/wireless/broadcom/brcm80211/brcmutil/
Dd11.c28 static u16 d11n_bw(enum brcmu_chan_bw bw) in d11n_bw() argument
30 switch (bw) { in d11n_bw()
43 if (ch->bw == BRCMU_CHAN_BW_20) in brcmu_d11n_encchspec()
52 0, d11n_bw(ch->bw)); in brcmu_d11n_encchspec()
60 static u16 d11ac_bw(enum brcmu_chan_bw bw) in d11ac_bw() argument
62 switch (bw) { in d11ac_bw()
79 if (ch->bw == BRCMU_CHAN_BW_20 || ch->sb == BRCMU_CHAN_SB_NONE) in brcmu_d11ac_encchspec()
87 0, d11ac_bw(ch->bw)); in brcmu_d11ac_encchspec()
105 ch->bw = BRCMU_CHAN_BW_20; in brcmu_d11n_decchspec()
109 ch->bw = BRCMU_CHAN_BW_40; in brcmu_d11n_decchspec()
[all …]
/drivers/media/dvb-frontends/
Ddib7000m.c316 static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw) in dib7000m_set_bandwidth() argument
320 if (!bw) in dib7000m_set_bandwidth()
321 bw = 8000; in dib7000m_set_bandwidth()
324 state->current_bandwidth = bw; in dib7000m_set_bandwidth()
334 timf = timf * (bw / 50) / 160; in dib7000m_set_bandwidth()
382 … dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw) in dib7000m_reset_pll_common() argument
384 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff)); in dib7000m_reset_pll_common()
385 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff)); in dib7000m_reset_pll_common()
386 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff)); in dib7000m_reset_pll_common()
387 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff)); in dib7000m_reset_pll_common()
[all …]
Ddib7000p.c373 static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw) in dib7000p_set_bandwidth() argument
378 state->current_bandwidth = bw; in dib7000p_set_bandwidth()
382 timf = state->cfg.bw->timf; in dib7000p_set_bandwidth()
388 timf = timf * (bw / 50) / 160; in dib7000p_set_bandwidth()
449 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; in dib7000p_reset_pll() local
453 …dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio <… in dib7000p_reset_pll()
458 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15)); in dib7000p_reset_pll()
461 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) | in dib7000p_reset_pll()
462 …(bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw-… in dib7000p_reset_pll()
467 …dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw-… in dib7000p_reset_pll()
[all …]
/drivers/net/wireless/realtek/rtw88/
Dphy.c1323 u8 bw, u8 rs, u8 ch, s8 pwr_limit) in rtw_phy_set_tx_power_limit() argument
1334 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX || in rtw_phy_set_tx_power_limit()
1338 regd, band, bw, rs, ch_idx, pwr_limit); in rtw_phy_set_tx_power_limit()
1343 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit; in rtw_phy_set_tx_power_limit()
1344 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx]; in rtw_phy_set_tx_power_limit()
1346 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww; in rtw_phy_set_tx_power_limit()
1348 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit; in rtw_phy_set_tx_power_limit()
1349 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx]; in rtw_phy_set_tx_power_limit()
1351 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww; in rtw_phy_set_tx_power_limit()
1358 u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht) in rtw_xref_5g_txpwr_lmt() argument
[all …]
/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c907 &context->bw_ctx.bw.dce)) in dce112_validate_bandwidth()
915 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce112_validate_bandwidth()
916 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce112_validate_bandwidth()
930 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, in dce112_validate_bandwidth()
931 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, in dce112_validate_bandwidth()
932 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce112_validate_bandwidth()
933 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce112_validate_bandwidth()
934 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, in dce112_validate_bandwidth()
935 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, in dce112_validate_bandwidth()
936 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, in dce112_validate_bandwidth()
[all …]
/drivers/media/usb/dvb-usb-v2/
Dmxl111sf-tuner.c79 u8 bw) in mxl111sf_calc_phy_tune_regs() argument
84 switch (bw) { in mxl111sf_calc_phy_tune_regs()
186 static int mxl1x1sf_tune_rf(struct dvb_frontend *fe, u32 freq, u8 bw) in mxl1x1sf_tune_rf() argument
193 mxl_dbg("(freq = %d, bw = 0x%x)", freq, bw); in mxl1x1sf_tune_rf()
206 reg_ctrl_array = mxl111sf_calc_phy_tune_regs(freq, bw); in mxl1x1sf_tune_rf()
268 u8 bw; in mxl111sf_tuner_set_params() local
275 bw = 0; /* ATSC */ in mxl111sf_tuner_set_params()
278 bw = 1; /* US CABLE */ in mxl111sf_tuner_set_params()
283 bw = 6; in mxl111sf_tuner_set_params()
286 bw = 7; in mxl111sf_tuner_set_params()
[all …]
/drivers/gpu/drm/amd/display/dc/core/
Ddc_debug.c352 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
353 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
354 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
355 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
356 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
357 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
360 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
361 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
362 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
363 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
204 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
210 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
223 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
254 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
269 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c987 &context->bw_ctx.bw.dce)) in dce110_validate_bandwidth()
997 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce110_validate_bandwidth()
998 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce110_validate_bandwidth()
1012 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1013 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1014 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1015 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1016 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1017 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1018 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, in dce110_validate_bandwidth()
[all …]
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c567 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
569 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
571 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
573 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
574 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
581 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
583 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
585 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
587 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
588 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
[all …]
/drivers/net/ethernet/intel/ice/
Dice_sched.c1990 static void ice_set_clear_cir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) in ice_set_clear_cir_bw() argument
1992 if (bw == ICE_SCHED_DFLT_BW) { in ice_set_clear_cir_bw()
1994 bw_t_info->cir_bw.bw = 0; in ice_set_clear_cir_bw()
1998 bw_t_info->cir_bw.bw = bw; in ice_set_clear_cir_bw()
2009 static void ice_set_clear_eir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) in ice_set_clear_eir_bw() argument
2011 if (bw == ICE_SCHED_DFLT_BW) { in ice_set_clear_eir_bw()
2013 bw_t_info->eir_bw.bw = 0; in ice_set_clear_eir_bw()
2023 bw_t_info->eir_bw.bw = bw; in ice_set_clear_eir_bw()
2034 static void ice_set_clear_shared_bw(struct ice_bw_type_info *bw_t_info, u32 bw) in ice_set_clear_shared_bw() argument
2036 if (bw == ICE_SCHED_DFLT_BW) { in ice_set_clear_shared_bw()
[all …]
/drivers/net/wireless/mediatek/mt7601u/
Dphy.c246 int bw = FIELD_GET(MT_RXWI_RATE_BW, rate); in mt7601u_phy_get_rssi() local
255 val -= lna[aux_lna][bw][lna_id]; in mt7601u_phy_get_rssi()
278 if (dev->bw != MT_BW_20) in mt7601u_set_bw_filter()
296 t = &bbp_mode_table[dev->temp_mode][dev->bw]; in mt7601u_load_bbp_temp_table_bw()
319 t[dev->bw].regs, t[dev->bw].n); in mt7601u_bbp_temp()
326 if (hw_chan != 14 || dev->bw != MT_BW_20) { in mt7601u_apply_ch14_fixup()
377 u8 bw; in __mt7601u_phy_set_channel() local
380 bw = MT_BW_20; in __mt7601u_phy_set_channel()
385 bw = MT_BW_40; in __mt7601u_phy_set_channel()
395 if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) { in __mt7601u_phy_set_channel()
[all …]
/drivers/net/wireless/ath/carl9170/
Dphy.c967 u32 freq, enum carl9170_bw bw) in carl9170_init_rf_bank4_pwr() argument
975 switch (bw) { in carl9170_init_rf_bank4_pwr()
1036 enum carl9170_bw bw) in carl9170_get_hw_dyn_params() argument
1052 return &carl9170_phy_freq_params[chanidx].params[bw]; in carl9170_get_hw_dyn_params()
1260 enum carl9170_bw bw, struct ar9170_calctl_edges edges[]) in carl9170_get_heavy_clip() argument
1271 if (bw == CARL9170_BW_40_BELOW || bw == CARL9170_BW_40_ABOVE) in carl9170_get_heavy_clip()
1291 static void carl9170_calc_ctl(struct ar9170 *ar, u32 freq, enum carl9170_bw bw) in carl9170_calc_ctl() argument
1366 freq, bw, EDGES(ctl_idx, 1)); in carl9170_calc_ctl()
1372 if (bw == CARL9170_BW_40_BELOW) in carl9170_calc_ctl()
1429 enum carl9170_bw bw) in carl9170_set_power_cal() argument
[all …]
/drivers/media/tuners/
Dmxl5007t.c381 enum mxl5007t_bw_mhz bw) in mxl5007t_set_bw_bits() argument
385 switch (bw) { in mxl5007t_set_bw_bits()
407 u32 rf_freq, enum mxl5007t_bw_mhz bw) in mxl5007t_calc_rf_tune_regs() argument
416 mxl5007t_set_bw_bits(state, bw); in mxl5007t_calc_rf_tune_regs()
530 enum mxl5007t_bw_mhz bw) in mxl5007t_tuner_rf_tune() argument
536 rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw); in mxl5007t_tuner_rf_tune()
604 enum mxl5007t_bw_mhz bw; in mxl5007t_set_params() local
612 bw = MxL_BW_6MHz; in mxl5007t_set_params()
616 bw = MxL_BW_6MHz; in mxl5007t_set_params()
623 bw = MxL_BW_6MHz; in mxl5007t_set_params()
[all …]
/drivers/net/wireless/mediatek/mt76/mt76x2/
Dusb_phy.c87 u8 channel = chan->hw_value, bw, bw_index; in mt76x2u_phy_set_channel() local
96 bw = 1; in mt76x2u_phy_set_channel()
110 bw = 2; in mt76x2u_phy_set_channel()
115 bw = 0; in mt76x2u_phy_set_channel()
123 mt76x2_configure_tx_delay(dev, chan->band, bw); in mt76x2u_phy_set_channel()
137 ret = mt76x2_mcu_set_channel(dev, channel, bw, bw_index, scan); in mt76x2u_phy_set_channel()
Dmcu.c15 int mt76x2_mcu_set_channel(struct mt76x02_dev *dev, u8 channel, u8 bw, in mt76x2_mcu_set_channel() argument
21 u8 bw; in mt76x2_mcu_set_channel() member
31 .bw = bw, in mt76x2_mcu_set_channel()
/drivers/memory/samsung/
Dexynos-srom.c72 u32 cs, bw; in exynos_srom_configure_bank() local
90 bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW); in exynos_srom_configure_bank()
91 bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank); in exynos_srom_configure_bank()
92 writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW); in exynos_srom_configure_bank()
/drivers/net/wireless/marvell/mwifiex/
Dcfp.c201 u8 bw = 0; in mwifiex_index_to_acs_data_rate() local
208 bw = (ht_info & 0xC) >> 2; in mwifiex_index_to_acs_data_rate()
214 rate = ac_mcs_rate_nss2[2 * (3 - bw) + gi][mcs_index]; in mwifiex_index_to_acs_data_rate()
216 rate = ac_mcs_rate_nss1[2 * (3 - bw) + gi][mcs_index]; in mwifiex_index_to_acs_data_rate()
219 bw = (ht_info & 0xC) >> 2; in mwifiex_index_to_acs_data_rate()
230 if ((bw == 1) || (bw == 0)) in mwifiex_index_to_acs_data_rate()
231 rate = mcs_rate[2 * (1 - bw) + gi][index]; in mwifiex_index_to_acs_data_rate()
/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Drate.h137 u32 bw = rspec_get_bw(rspec); in rspec_is40mhz() local
139 return bw == PHY_TXC1_BW_40MHZ || bw == PHY_TXC1_BW_40MHZ_DUP; in rspec_is40mhz()
236 bool mcsallow, u8 bw, u8 txstreams);
243 void brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset *rateset, u8 bw);
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clk_mgr.c227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
615 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
617 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
619 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
625 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
630 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
643 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
[all …]
/drivers/usb/host/
Dehci-dbg.c518 u8 *bw; in fill_bandwidth_buffer() local
536 bw = &ehci->bandwidth[i]; in fill_bandwidth_buffer()
539 i, bw[0], bw[1], bw[2], bw[3], in fill_bandwidth_buffer()
540 bw[4], bw[5], bw[6], bw[7]); in fill_bandwidth_buffer()
568 bw = &budget[i]; in fill_bandwidth_buffer()
571 i, bw[0], bw[1], bw[2], bw[3], in fill_bandwidth_buffer()
572 bw[4], bw[5], bw[6], bw[7]); in fill_bandwidth_buffer()
/drivers/net/ethernet/intel/ixgbe/
Dixgbe_dcb.c21 static s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill, in ixgbe_ieee_credits() argument
32 if (bw[i] < min_percent && bw[i]) in ixgbe_ieee_credits()
33 min_percent = bw[i]; in ixgbe_ieee_credits()
40 int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL); in ixgbe_ieee_credits()
46 max[i] = bw[i] ? (bw[i] * MAX_CREDIT)/100 : min_credit; in ixgbe_ieee_credits()
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Ddp.c234 ior->dp.nr, ior->dp.bw * 27); in nvkm_dp_train_links()
244 while ((ior->dp.bw * 2700) < nvbios_rd16(bios, lnkcmp)) in nvkm_dp_train_links()
248 while (ior->dp.bw < nvbios_rd08(bios, lnkcmp)) in nvkm_dp_train_links()
272 sink[0] = ior->dp.bw; in nvkm_dp_train_links()
329 u8 bw; member
368 if (cfg->nr <= outp_nr && cfg->bw <= outp_bw) { in nvkm_dp_train()
373 (cfg->nr <= sink_nr && cfg->bw <= sink_bw)) in nvkm_dp_train()
395 failsafe->nr, failsafe->bw * 27); in nvkm_dp_train()
399 if ((cfg->nr > outp_nr || cfg->bw > outp_bw || in nvkm_dp_train()
400 cfg->nr > sink_nr || cfg->bw > sink_bw)) { in nvkm_dp_train()
[all …]

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