Searched refs:clk_lane_reg1 (Results 1 – 1 of 1) sorted by relevance
100 u8 clk_lane_reg1; member404 bridge->r.clk_lane_reg1 |= (2000000000 / link_freq) << 2; in mipid02_configure_from_rx_speed()420 bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE; in mipid02_configure_clk_lane()564 bridge->r.clk_lane_reg1); in mipid02_stream_enable()