| /drivers/gpu/drm/msm/dp/ |
| D | dp_parser.c | 104 const char *clk_name) in dp_parser_check_prefix() argument
106 return !strncmp(clk_prefix, clk_name, strlen(clk_prefix)); in dp_parser_check_prefix()
113 const char *clk_name; in dp_parser_init_clk_data() local
127 "clock-names", i, &clk_name); in dp_parser_init_clk_data()
131 if (dp_parser_check_prefix("core", clk_name)) in dp_parser_init_clk_data()
134 if (dp_parser_check_prefix("ctrl", clk_name)) in dp_parser_init_clk_data()
137 if (dp_parser_check_prefix("stream", clk_name)) in dp_parser_init_clk_data()
193 const char *clk_name; in dp_parser_clock() local
213 i, &clk_name); in dp_parser_clock()
218 if (dp_parser_check_prefix("core", clk_name) && in dp_parser_clock()
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| /drivers/clk/zynqmp/ |
| D | pll.c | 52 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_get_mode() local
59 __func__, clk_name, ret); in zynqmp_pll_get_mode()
73 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_mode() local
85 __func__, clk_name, ret); in zynqmp_pll_set_mode()
135 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_recalc_rate() local
144 __func__, clk_name, ret); in zynqmp_pll_recalc_rate()
172 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_rate() local
190 clk_name); in zynqmp_pll_set_rate()
193 __func__, clk_name, ret); in zynqmp_pll_set_rate()
204 __func__, clk_name, ret); in zynqmp_pll_set_rate()
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| D | clk-gate-zynqmp.c | 37 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_enable() local
45 __func__, clk_name, ret); in zynqmp_clk_gate_enable()
57 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_disable() local
65 __func__, clk_name, ret); in zynqmp_clk_gate_disable()
77 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_is_enabled() local
84 __func__, clk_name, ret); in zynqmp_clk_gate_is_enabled()
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| D | clkc.c | 71 char clk_name[MAX_NAME_LEN]; member
160 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) in zynqmp_get_clock_name() argument
166 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); in zynqmp_get_clock_name()
558 static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name, in zynqmp_register_clk_topology() argument
578 clk_out[j] = kasprintf(GFP_KERNEL, "%s%s", clk_name, in zynqmp_register_clk_topology()
581 clk_out[j] = kasprintf(GFP_KERNEL, "%s", clk_name); in zynqmp_register_clk_topology()
593 __func__, clk_dev_id, clk_name, in zynqmp_register_clk_topology()
618 char clk_name[MAX_NAME_LEN]; in zynqmp_register_clocks() local
621 if (zynqmp_get_clock_name(i, clk_name)) in zynqmp_register_clocks()
635 clock[i].clk_name); in zynqmp_register_clocks()
[all …]
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| D | divider.c | 82 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_recalc_rate() local
92 __func__, clk_name, ret); in zynqmp_clk_divider_recalc_rate()
105 clk_name); in zynqmp_clk_divider_recalc_rate()
125 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_round_rate() local
138 __func__, clk_name, ret); in zynqmp_clk_divider_round_rate()
172 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_set_rate() local
194 __func__, clk_name, ret); in zynqmp_clk_divider_set_rate()
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| D | clk-mux-zynqmp.c | 46 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_mux_get_parent() local
55 __func__, clk_name, ret); in zynqmp_clk_mux_get_parent()
70 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_mux_set_parent() local
78 __func__, clk_name, ret); in zynqmp_clk_mux_set_parent()
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| /drivers/mailbox/ |
| D | qcom-apcs-ipc-mailbox.c | 29 char *clk_name; member
33 .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
37 .offset = 8, .clk_name = NULL
41 .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
45 .offset = 8, .clk_name = NULL
49 .offset = 16, .clk_name = NULL
53 .offset = 8, .clk_name = NULL
57 .offset = 8, .clk_name = NULL
61 .offset = 12, .clk_name = NULL
128 if (apcs_data->clk_name) { in qcom_apcs_ipc_probe()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_io_util.c | 32 clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name); in msm_dss_get_clk()
37 clk_arry[i].clk_name, rc); in msm_dss_get_clk()
63 clk_arry[i].clk_name, in msm_dss_clk_set_rate()
71 clk_arry[i].clk_name, rc); in msm_dss_clk_set_rate()
78 clk_arry[i].clk_name); in msm_dss_clk_set_rate()
95 clk_arry[i].clk_name); in msm_dss_enable_clk()
101 clk_arry[i].clk_name, rc); in msm_dss_enable_clk()
113 clk_arry[i].clk_name); in msm_dss_enable_clk()
154 strlcpy(mp->clk_config[i].clk_name, clock_name, in msm_dss_parse_clock()
155 sizeof(mp->clk_config[i].clk_name)); in msm_dss_parse_clock()
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| /drivers/clk/sunxi/ |
| D | clk-a10-pll2.c | 41 const char *clk_name = node->name, *parent; in sun4i_pll2_setup() local
121 SUN4I_A10_PLL2_1X, &clk_name); in sun4i_pll2_setup()
122 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
136 SUN4I_A10_PLL2_2X, &clk_name); in sun4i_pll2_setup()
137 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
145 SUN4I_A10_PLL2_4X, &clk_name); in sun4i_pll2_setup()
146 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
154 SUN4I_A10_PLL2_8X, &clk_name); in sun4i_pll2_setup()
155 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
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| D | clk-sun4i-pll3.c | 23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
36 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_pll3_setup()
57 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_pll3_setup()
64 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_pll3_setup()
71 clk_name); in sun4i_a10_pll3_setup()
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| D | clk-sunxi.c | 655 const char *clk_name = node->name; in sunxi_mux_clk_setup() local
667 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_mux_clk_setup()
673 clk = clk_register_mux(NULL, clk_name, parents, i, in sunxi_mux_clk_setup()
680 clk_name, PTR_ERR(clk)); in sunxi_mux_clk_setup()
686 __func__, clk_name); in sunxi_mux_clk_setup()
779 const char *clk_name = node->name; in sunxi_divider_clk_setup() local
791 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_divider_clk_setup()
797 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0, in sunxi_divider_clk_setup()
803 __func__, clk_name, PTR_ERR(clk)); in sunxi_divider_clk_setup()
809 __func__, clk_name); in sunxi_divider_clk_setup()
[all …]
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| D | clk-sun4i-display.c | 105 const char *clk_name = node->name; in sun4i_a10_display_init() local
115 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_display_init()
119 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_display_init()
125 pr_err("%s: Could not retrieve the parents\n", clk_name); in sun4i_a10_display_init()
157 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_display_init()
165 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_display_init()
171 pr_err("%s: Couldn't register DT provider\n", clk_name); in sun4i_a10_display_init()
198 clk_name); in sun4i_a10_display_init()
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| D | clk-sun4i-tcon-ch1.c | 227 const char *clk_name = node->name; in tcon_ch1_setup() local
235 of_property_read_string(node, "clock-output-names", &clk_name); in tcon_ch1_setup()
239 pr_err("%s: Could not map the clock registers\n", clk_name); in tcon_ch1_setup()
245 pr_err("%s Could not retrieve the parents\n", clk_name); in tcon_ch1_setup()
253 init.name = clk_name; in tcon_ch1_setup()
265 pr_err("%s: Couldn't register the clock\n", clk_name); in tcon_ch1_setup()
271 pr_err("%s: Couldn't register our clock provider\n", clk_name); in tcon_ch1_setup()
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| D | clk-a10-codec.c | 17 const char *clk_name = node->name, *parent_name; in sun4i_codec_clk_setup() local
24 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_codec_clk_setup()
27 clk = clk_register_gate(NULL, clk_name, parent_name, in sun4i_codec_clk_setup()
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| /drivers/clk/pxa/ |
| D | clk-pxa.h | 19 #define MUX_RO_RATE_RO_OPS(name, clk_name) \ argument
31 return clk_register_composite(NULL, clk_name, \
39 #define RATE_RO_OPS(name, clk_name) \ argument
46 return clk_register_composite(NULL, clk_name, \
54 #define RATE_OPS(name, clk_name) \ argument
63 return clk_register_composite(NULL, clk_name, \
71 #define MUX_OPS(name, clk_name, flags) \ argument
80 return clk_register_composite(NULL, clk_name, \
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| /drivers/staging/clocking-wizard/ |
| D | clk-xlnx-clock-wizard.c | 136 const char *clk_name; in clk_wzrd_probe() local
195 clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev)); in clk_wzrd_probe()
196 if (!clk_name) { in clk_wzrd_probe()
201 (&pdev->dev, clk_name, in clk_wzrd_probe()
204 kfree(clk_name); in clk_wzrd_probe()
214 clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); in clk_wzrd_probe()
215 if (!clk_name) { in clk_wzrd_probe()
221 (&pdev->dev, clk_name, in clk_wzrd_probe()
245 (&pdev->dev, clkout_name, clk_name, 0, 1, reg); in clk_wzrd_probe()
258 kfree(clk_name); in clk_wzrd_probe()
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| /drivers/clk/h8300/ |
| D | clk-div.c | 20 const char *clk_name = node->name; in h8300_div_clk_setup() local
28 pr_err("%s: no parent found\n", clk_name); in h8300_div_clk_setup()
34 pr_err("%s: failed to map divide register\n", clk_name); in h8300_div_clk_setup()
43 hw = clk_hw_register_divider(NULL, clk_name, parent_name, in h8300_div_clk_setup()
51 __func__, clk_name, PTR_ERR(hw)); in h8300_div_clk_setup()
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| D | clk-h8s2678.c | 89 const char *clk_name = node->name; in h8s2678_pll_clk_setup() local
97 pr_err("%s: no parent found\n", clk_name); in h8s2678_pll_clk_setup()
108 pr_err("%s: failed to map divide register\n", clk_name); in h8s2678_pll_clk_setup()
114 pr_err("%s: failed to map multiply register\n", clk_name); in h8s2678_pll_clk_setup()
119 init.name = clk_name; in h8s2678_pll_clk_setup()
129 __func__, clk_name, ret); in h8s2678_pll_clk_setup()
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| /drivers/clk/mvebu/ |
| D | clk-cpu.c | 36 const char *clk_name; member
198 char *clk_name = kzalloc(5, GFP_KERNEL); in of_cpu_clk_setup() local
201 if (WARN_ON(!clk_name)) in of_cpu_clk_setup()
208 sprintf(clk_name, "cpu%d", cpu); in of_cpu_clk_setup()
211 cpuclk[cpu].clk_name = clk_name; in of_cpu_clk_setup()
218 init.name = cpuclk[cpu].clk_name; in of_cpu_clk_setup()
237 kfree(cpuclk[ncpus].clk_name); in of_cpu_clk_setup()
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| /drivers/clk/ |
| D | clk-nspire.c | 69 const char *clk_name = node->name; in nspire_ahbdiv_setup() local
81 of_property_read_string(node, "clock-output-names", &clk_name); in nspire_ahbdiv_setup()
84 hw = clk_hw_register_fixed_factor(NULL, clk_name, parent_name, 0, in nspire_ahbdiv_setup()
111 const char *clk_name = node->name; in nspire_clk_setup() local
122 of_property_read_string(node, "clock-output-names", &clk_name); in nspire_clk_setup()
124 hw = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0, in nspire_clk_setup()
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| D | clk-xgene.c | 171 const char *clk_name = np->full_name; in xgene_pllclk_init() local
181 of_property_read_string(np, "clock-output-names", &clk_name); in xgene_pllclk_init()
183 clk_name, of_clk_get_parent_name(np, 0), in xgene_pllclk_init()
188 clk_register_clkdev(clk, clk_name, NULL); in xgene_pllclk_init()
189 pr_debug("Add %s clock PLL\n", clk_name); in xgene_pllclk_init()
380 const char *clk_name = np->full_name; in xgene_pmdclk_init() local
403 of_property_read_string(np, "clock-output-names", &clk_name); in xgene_pmdclk_init()
408 clk = xgene_register_clk_pmd(NULL, clk_name, in xgene_pmdclk_init()
415 clk_register_clkdev(clk, clk_name, NULL); in xgene_pmdclk_init()
416 pr_debug("Add %s clock\n", clk_name); in xgene_pmdclk_init()
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| /drivers/clk/keystone/ |
| D | pll.c | 254 const char *clk_name = node->name; in of_pll_div_clk_init() local
256 of_property_read_string(node, "clock-output-names", &clk_name); in of_pll_div_clk_init()
282 clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, in of_pll_div_clk_init()
285 pr_err("%s: error registering divider %s\n", __func__, clk_name); in of_pll_div_clk_init()
304 const char *clk_name = node->name; in of_pll_mux_clk_init() local
306 of_property_read_string(node, "clock-output-names", &clk_name); in of_pll_mux_clk_init()
329 clk = clk_register_mux(NULL, clk_name, (const char **)&parents, in of_pll_mux_clk_init()
333 pr_err("%s: error registering mux %s\n", __func__, clk_name); in of_pll_mux_clk_init()
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| /drivers/clk/ti/ |
| D | clockdomain.c | 110 const char *clk_name; in omap2_init_clk_clkdm() local
115 clk_name = __clk_get_name(hw->clk); in omap2_init_clk_clkdm()
120 clk_name, clk->clkdm_name); in omap2_init_clk_clkdm()
124 clk_name, clk->clkdm_name); in omap2_init_clk_clkdm()
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| /drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_10nm.c | 662 char clk_name[32], parent[32], vco_name[32]; in pll_10nm_register() local
691 snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); in pll_10nm_register()
694 hw = clk_hw_register_divider(dev, clk_name, in pll_10nm_register()
706 snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id); in pll_10nm_register()
710 hw = clk_hw_register_divider(dev, clk_name, parent, in pll_10nm_register()
723 snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id); in pll_10nm_register()
727 hw = clk_hw_register_fixed_factor(dev, clk_name, parent, in pll_10nm_register()
737 snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); in pll_10nm_register()
740 hw = clk_hw_register_fixed_factor(dev, clk_name, parent, in pll_10nm_register()
749 snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); in pll_10nm_register()
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| D | dsi_pll_7nm.c | 688 char clk_name[32], parent[32], vco_name[32]; in pll_7nm_register() local
717 snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->id); in pll_7nm_register()
720 hw = clk_hw_register_divider(dev, clk_name, in pll_7nm_register()
732 snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->id); in pll_7nm_register()
736 hw = clk_hw_register_divider(dev, clk_name, parent, in pll_7nm_register()
749 snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->id); in pll_7nm_register()
753 hw = clk_hw_register_fixed_factor(dev, clk_name, parent, in pll_7nm_register()
763 snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->id); in pll_7nm_register()
766 hw = clk_hw_register_fixed_factor(dev, clk_name, parent, in pll_7nm_register()
775 snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->id); in pll_7nm_register()
[all …]
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