Searched refs:control_value (Results 1 – 4 of 4) sorted by relevance
| /drivers/gpu/drm/hisilicon/hibmc/ |
| D | hibmc_drm_drv.c | 128 unsigned int control_value = 0; in hibmc_set_power_mode() local
138 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL); in hibmc_set_power_mode()
139 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK | in hibmc_set_power_mode()
141 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode); in hibmc_set_power_mode()
142 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input); in hibmc_set_power_mode()
143 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL); in hibmc_set_power_mode()
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| /drivers/mmc/host/ |
| D | sdhci-pci-gli.c | 154 u32 control_value; in gli_set_9750() local
164 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
203 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; in gli_set_9750()
204 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; in gli_set_9750()
205 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, in gli_set_9750()
207 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, in gli_set_9750()
219 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; in gli_set_9750()
220 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, in gli_set_9750()
222 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
228 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; in gli_set_9750()
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| /drivers/gpu/drm/i915/gt/ |
| D | intel_mocs.c | 33 u32 control_value; member
88 .control_value = __control_value, \
383 return table->table[index].control_value; in get_entry_control()
385 return table->table[I915_MOCS_PTE].control_value; in get_entry_control()
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| /drivers/net/ethernet/qlogic/netxen/ |
| D | netxen_nic.h | 1421 u32 control_value; member
1496 u32 control_value; member
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