Home
last modified time | relevance | path

Searched refs:cpu_base (Results 1 – 9 of 9) sorted by relevance

/drivers/irqchip/
Dirq-gic.c71 union gic_base cpu_base; member
145 #define gic_data_cpu_base(d) __get_base(&(d)->cpu_base)
148 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
340 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq() local
343 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); in gic_handle_irq()
350 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); in gic_handle_irq()
450 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_cpu_if_up() local
458 if (gic_check_gicv2(cpu_base)) in gic_cpu_if_up()
460 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4); in gic_cpu_if_up()
465 bypass = readl(cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
[all …]
Dirq-hip04.c54 void __iomem *cpu_base; member
80 return hip04_data->cpu_base; in hip04_cpu_base()
202 void __iomem *cpu_base = hip04_data.cpu_base; in hip04_handle_irq() local
205 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); in hip04_handle_irq()
271 void __iomem *base = intc->cpu_base; in hip04_irq_cpu_init()
367 hip04_data.cpu_base = of_iomap(node, 1); in hip04_of_init()
368 WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n"); in hip04_of_init()
/drivers/net/ethernet/broadcom/
Dbgmac.c124 dma_desc = &ring->cpu_base[i]; in bgmac_dma_tx_add_buf()
217 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); in bgmac_dma_tx_add()
257 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0); in bgmac_dma_tx_free()
258 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); in bgmac_dma_tx_free()
380 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; in bgmac_dma_rx_setup_desc()
529 struct bgmac_dma_desc *dma_desc = ring->cpu_base; in bgmac_dma_tx_ring_free()
579 if (!ring->cpu_base) in bgmac_dma_ring_desc_free()
584 dma_free_coherent(dma_dev, size, ring->cpu_base, in bgmac_dma_ring_desc_free()
637 ring->cpu_base = dma_alloc_coherent(dma_dev, size, in bgmac_dma_alloc()
640 if (!ring->cpu_base) { in bgmac_dma_alloc()
[all …]
Dtg3.c3587 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) in tg3_pause_cpu() argument
3593 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_pause_cpu()
3594 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); in tg3_pause_cpu()
3595 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT) in tg3_pause_cpu()
3623 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) in tg3_resume_cpu() argument
3625 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_resume_cpu()
3626 tw32_f(cpu_base + CPU_MODE, 0x00000000); in tg3_resume_cpu()
3636 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) in tg3_halt_cpu() argument
3640 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); in tg3_halt_cpu()
3648 if (cpu_base == RX_CPU_BASE) { in tg3_halt_cpu()
[all …]
Dbgmac.h465 struct bgmac_dma_desc *cpu_base; member
/drivers/infiniband/hw/hns/
Dhns_roce_hem.c1227 void *cpu_base; in hem_list_alloc_root_bt() local
1268 cpu_base = root_hem->addr + total * BA_BYTE_LEN; in hem_list_alloc_root_bt()
1282 hem_list_assign_bt(hr_dev, hem, cpu_base, phy_base); in hem_list_alloc_root_bt()
1297 hem_list_link_bt(hr_dev, cpu_base + offset, in hem_list_alloc_root_bt()
1402 void *cpu_base = NULL; in hns_roce_hem_list_find_mtt() local
1409 cpu_base = hem->addr + nr * BA_BYTE_LEN; in hns_roce_hem_list_find_mtt()
1422 return cpu_base; in hns_roce_hem_list_find_mtt()
/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_srv.c326 uint8_t *cpu_base; in dmub_srv_calc_mem_info() local
338 cpu_base = (uint8_t *)params->cpu_fb_addr; in dmub_srv_calc_mem_info()
345 out->fb[i].cpu_addr = cpu_base + reg->base; in dmub_srv_calc_mem_info()
/drivers/media/platform/qcom/venus/
Dcore.h161 void __iomem *cpu_base; member
Dcore.c217 core->cpu_base = core->base + CPU_BASE; in venus_assign_register_offsets()