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Searched refs:cpuclk (Results 1 – 5 of 5) sorted by relevance

/drivers/clk/rockchip/
Dclk-cpu.c72 struct rockchip_cpuclk *cpuclk, unsigned long rate) in rockchip_get_cpuclk_settings() argument
75 cpuclk->rate_table; in rockchip_get_cpuclk_settings()
78 for (i = 0; i < cpuclk->rate_count; i++) { in rockchip_get_cpuclk_settings()
89 struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw); in rockchip_cpuclk_recalc_rate() local
90 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_recalc_rate()
91 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_recalc_rate()
102 static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, in rockchip_cpuclk_set_dividers() argument
116 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
120 static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, in rockchip_cpuclk_pre_rate_change() argument
123 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_pre_rate_change()
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/drivers/clk/samsung/
Dclk-cpu.c150 struct exynos_cpuclk *cpuclk, void __iomem *base) in exynos_cpuclk_pre_rate_change() argument
152 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; in exynos_cpuclk_pre_rate_change()
153 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); in exynos_cpuclk_pre_rate_change()
165 spin_lock_irqsave(cpuclk->lock, flags); in exynos_cpuclk_pre_rate_change()
173 if (cpuclk->flags & CLK_CPU_HAS_DIV1) { in exynos_cpuclk_pre_rate_change()
194 if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { in exynos_cpuclk_pre_rate_change()
215 if (cpuclk->flags & CLK_CPU_HAS_DIV1) { in exynos_cpuclk_pre_rate_change()
221 spin_unlock_irqrestore(cpuclk->lock, flags); in exynos_cpuclk_pre_rate_change()
227 struct exynos_cpuclk *cpuclk, void __iomem *base) in exynos_cpuclk_post_rate_change() argument
229 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; in exynos_cpuclk_post_rate_change()
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/drivers/clk/mvebu/
Dclk-cpu.c51 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_recalc_rate() local
54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate()
55 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; in clk_cpu_recalc_rate()
78 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_off_set_rate() local
83 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) in clk_cpu_off_set_rate()
84 & (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8)))) in clk_cpu_off_set_rate()
85 | (div << (cpuclk->cpu * 8)); in clk_cpu_off_set_rate()
86 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_off_set_rate()
88 reload_mask = 1 << (20 + cpuclk->cpu); in clk_cpu_off_set_rate()
90 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_off_set_rate()
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/drivers/cpufreq/
Dsh-cpufreq.c48 struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu); in __sh_cpufreq_target() local
59 freq = clk_round_rate(cpuclk, target->freq * 1000); in __sh_cpufreq_target()
71 clk_set_rate(cpuclk, freq); in __sh_cpufreq_target()
92 struct clk *cpuclk = &per_cpu(sh_cpuclk, policy->cpu); in sh_cpufreq_verify() local
95 freq_table = cpuclk->nr_freqs ? cpuclk->freq_table : NULL; in sh_cpufreq_verify()
101 policy->min = (clk_round_rate(cpuclk, 1) + 500) / 1000; in sh_cpufreq_verify()
102 policy->max = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000; in sh_cpufreq_verify()
111 struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu); in sh_cpufreq_cpu_init() local
117 cpuclk = clk_get(dev, "cpu_clk"); in sh_cpufreq_cpu_init()
118 if (IS_ERR(cpuclk)) { in sh_cpufreq_cpu_init()
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/drivers/clk/qcom/
Dclk-cpu-8996.c208 struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); in clk_cpu_8996_mux_get_parent() local
209 u32 mask = GENMASK(cpuclk->width - 1, 0); in clk_cpu_8996_mux_get_parent()
212 regmap_read(clkr->regmap, cpuclk->reg, &val); in clk_cpu_8996_mux_get_parent()
213 val >>= cpuclk->shift; in clk_cpu_8996_mux_get_parent()
221 struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); in clk_cpu_8996_mux_set_parent() local
222 u32 mask = GENMASK(cpuclk->width + cpuclk->shift - 1, cpuclk->shift); in clk_cpu_8996_mux_set_parent()
226 val <<= cpuclk->shift; in clk_cpu_8996_mux_set_parent()
228 return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val); in clk_cpu_8996_mux_set_parent()
234 struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); in clk_cpu_8996_mux_determine_rate() local
235 struct clk_hw *parent = cpuclk->pll; in clk_cpu_8996_mux_determine_rate()
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