Searched refs:cw0 (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_dcn30.c | 84 const struct dmub_window *cw0, in dmub_dcn30_backdoor_load() argument
96 dmub_dcn30_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn30_backdoor_load()
100 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn30_backdoor_load()
102 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, in dmub_dcn30_backdoor_load()
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| D | dmub_dcn20.c | 143 const struct dmub_window *cw0, in dmub_dcn20_backdoor_load() argument
155 dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn20_backdoor_load()
159 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn20_backdoor_load()
161 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, in dmub_dcn20_backdoor_load()
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| D | dmub_srv.c | 404 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local
415 cw0.offset.quad_part = inst_fb->gpu_addr; in dmub_srv_hw_init()
416 cw0.region.base = DMUB_CW0_BASE; in dmub_srv_hw_init()
417 cw0.region.top = cw0.region.base + inst_fb->size - 1; in dmub_srv_hw_init()
431 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); in dmub_srv_hw_init()
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| D | dmub_dcn30.h | 38 const struct dmub_window *cw0,
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| D | dmub_dcn20.h | 166 const struct dmub_window *cw0,
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| /drivers/gpu/drm/amd/display/dmub/ |
| D | dmub_srv.h | 248 const struct dmub_window *cw0,
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