Searched refs:cw3 (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_dcn30.c | 120 const struct dmub_window *cw3, in dmub_dcn30_setup_windows() argument
145 offset = cw3->offset; in dmub_dcn30_setup_windows()
149 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); in dmub_dcn30_setup_windows()
151 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, in dmub_dcn30_setup_windows()
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| D | dmub_dcn20.c | 179 const struct dmub_window *cw3, in dmub_dcn20_setup_windows() argument
206 dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset); in dmub_dcn20_setup_windows()
210 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); in dmub_dcn20_setup_windows()
212 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, in dmub_dcn20_setup_windows()
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| D | dmub_srv.c | 404 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local
443 cw3.offset.quad_part = bios_fb->gpu_addr; in dmub_srv_hw_init()
444 cw3.region.base = DMUB_CW3_BASE; in dmub_srv_hw_init()
445 cw3.region.top = cw3.region.base + bios_fb->size; in dmub_srv_hw_init()
467 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, in dmub_srv_hw_init()
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| D | dmub_dcn30.h | 43 const struct dmub_window *cw3,
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| D | dmub_dcn20.h | 171 const struct dmub_window *cw3,
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| /drivers/gpu/drm/amd/display/dmub/ |
| D | dmub_srv.h | 253 const struct dmub_window *cw3,
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