Searched refs:cw5 (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_dcn30.c | 122 const struct dmub_window *cw5, in dmub_dcn30_setup_windows() argument
173 offset = cw5->offset; in dmub_dcn30_setup_windows()
177 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn30_setup_windows()
179 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn30_setup_windows()
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| D | dmub_dcn20.c | 181 const struct dmub_window *cw5, in dmub_dcn20_setup_windows() argument
235 dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset); in dmub_dcn20_setup_windows()
239 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn20_setup_windows()
241 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn20_setup_windows()
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| D | dmub_srv.c | 404 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local
454 cw5.offset.quad_part = tracebuff_fb->gpu_addr; in dmub_srv_hw_init()
455 cw5.region.base = DMUB_CW5_BASE; in dmub_srv_hw_init()
456 cw5.region.top = cw5.region.base + tracebuff_fb->size; in dmub_srv_hw_init()
468 &cw5, &cw6); in dmub_srv_hw_init()
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| D | dmub_dcn30.h | 45 const struct dmub_window *cw5,
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| D | dmub_dcn20.h | 173 const struct dmub_window *cw5,
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| /drivers/gpu/drm/amd/display/dmub/ |
| D | dmub_srv.h | 255 const struct dmub_window *cw5,
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