Searched refs:div0 (Results 1 – 8 of 8) sorted by relevance
| /drivers/clk/samsung/ |
| D | clk-cpu.c | 140 unsigned long div0; in exynos_set_safe_div() local
142 div0 = readl(base + E4210_DIV_CPU0); in exynos_set_safe_div()
143 div0 = (div0 & ~mask) | (div & mask); in exynos_set_safe_div()
144 writel(div0, base + E4210_DIV_CPU0); in exynos_set_safe_div()
155 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
172 div0 = cfg_data->div0; in exynos_cpuclk_pre_rate_change()
203 div0 |= alt_div; in exynos_cpuclk_pre_rate_change()
212 writel(div0, base + E4210_DIV_CPU0); in exynos_cpuclk_pre_rate_change()
251 div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK); in exynos_cpuclk_post_rate_change()
268 unsigned long div0; in exynos5433_set_safe_div() local
[all …]
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| D | clk-cpu.h | 27 unsigned long div0; member
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| /drivers/clk/uniphier/ |
| D | clk-uniphier.h | 110 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \ argument
111 UNIPHIER_CLK_DIV(parent, div0), \
114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument
115 UNIPHIER_CLK_DIV2(parent, div0, div1), \
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
119 UNIPHIER_CLK_DIV2(parent, div0, div1), \
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gf100.c | 278 u32 src0, div0, div1D, div1P = 0; in calc_clk() local
286 clk0 = calc_src(clk, idx, freq, &src0, &div0); in calc_clk()
301 if (div0) { in calc_clk()
303 info->ddiv |= div0 << 8; in calc_clk()
304 info->ddiv |= div0; in calc_clk()
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| D | gk104.c | 292 u32 src0, div0, div1D, div1P = 0; in calc_clk() local
300 clk0 = calc_src(clk, idx, freq, &src0, &div0); in calc_clk()
315 if (div0) { in calc_clk()
317 info->ddiv |= div0; in calc_clk()
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| /drivers/clk/x86/ |
| D | clk-cgu.c | 395 unsigned int div0, div1, exdiv; in lgm_clk_ddiv_recalc_rate() local
398 div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg, in lgm_clk_ddiv_recalc_rate()
405 do_div(prate, div0); in lgm_clk_ddiv_recalc_rate()
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| /drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 1436 struct clk_hw_proto0 *mux0, *div0, *gate0; in lpc32xx_clk_register() local
1439 div0 = clk_hw->hw1.div; in lpc32xx_clk_register()
1445 if (div0) { in lpc32xx_clk_register()
1446 dops = div0->ops; in lpc32xx_clk_register()
1447 div_hw = &div0->clk.hw; in lpc32xx_clk_register()
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| /drivers/i2c/busses/ |
| D | i2c-sprd.c | 339 u32 div0 = I2C_ADDR_DVD0_CALC(high, low); in sprd_i2c_set_clk() local
342 writel(div0, i2c_dev->base + ADDR_DVD0); in sprd_i2c_set_clk()
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