Home
last modified time | relevance | path

Searched refs:div_width (Results 1 – 13 of 13) sorted by relevance

/drivers/clk/rockchip/
Dclk.h371 int div_shift, int div_width,
416 u8 div_width; member
439 .div_width = dw, \
461 .div_width = dw, \
479 .div_width = dw, \
497 .div_width = dw, \
537 .div_width = dw, \
556 .div_width = dw, \
572 .div_width = 16, \
589 .div_width = 16, \
[all …]
Dclk-ddr.c22 int div_width; member
94 int div_shift, int div_width, in rockchip_clk_register_ddrclk() argument
130 ddrclk->div_width = div_width; in rockchip_clk_register_ddrclk()
Dclk.c41 int div_offset, u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_branch() argument
82 if (div_width > 0) { in rockchip_clk_register_branch()
95 div->width = div_width; in rockchip_clk_register_branch()
474 list->div_shift, list->div_width, in rockchip_clk_register_branches()
481 list->div_shift, list->div_width, in rockchip_clk_register_branches()
499 list->div_width, list->div_flags, in rockchip_clk_register_branches()
517 list->div_offset, list->div_shift, list->div_width, in rockchip_clk_register_branches()
541 list->div_shift, list->div_width, in rockchip_clk_register_branches()
551 list->div_width, list->div_flags, in rockchip_clk_register_branches()
Dclk-half-divider.c163 u8 div_shift, u8 div_width, in rockchip_clk_register_halfdiv() argument
202 if (div_width > 0) { in rockchip_clk_register_halfdiv()
210 div->width = div_width; in rockchip_clk_register_halfdiv()
/drivers/clk/x86/
Dclk-cgu.h183 u8 div_width; member
233 .div_width = _width, \
273 .div_width = _width, \
293 .div_width = _width, \
Dclk-cgu.c31 list->div_width, list->div_val); in lgm_clk_register_fixed()
200 u8 width = list->div_width; in lgm_clk_register_divider()
252 list->div_width, list->div_val); in lgm_clk_register_fixed_factor()
/drivers/clk/mediatek/
Dclk-mtk.h185 unsigned char div_width; member
196 .div_width = _width, \
Dclk-mt8167.c663 .div_width = _width, \
693 .div_width = _width, \
Dclk-mtk.c277 mcd->div_width, mcd->clk_divider_flags, lock); in mtk_clk_register_dividers()
Dclk-mt8516.c473 .div_width = _width, \
/drivers/clk/socfpga/
Dstratix10-clk.h57 u8 div_width; member
Dclk-gate-s10.c92 socfpga_clk->width = clks->div_width; in s10_register_gate()
/drivers/clk/
Dclk-bm1880.c121 s8 div_width; member
153 .div_width = _div_width, \
813 div_hws->div.width = clks->div_width; in bm1880_clk_register_composite()