Searched refs:divsel (Results 1 – 2 of 2) sorted by relevance
| /drivers/mfd/ |
| D | db8500-prcmu.c | 505 u32 divsel; member
512 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
517 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
1350 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << in request_dsiclk()
1504 u32 divsel; in dsiclk_rate() local
1507 divsel = readl(PRCM_DSI_PLLOUT_SEL); in dsiclk_rate()
1508 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); in dsiclk_rate()
1510 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) in dsiclk_rate()
1511 divsel = dsiclk[n].divsel; in dsiclk_rate()
1513 dsiclk[n].divsel = divsel; in dsiclk_rate()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_display.c | 5644 u32 divsel, phaseinc, auxdiv, phasedir = 0; in lpt_program_iclkip() local
5662 divsel = (desired_divisor / iclk_pi_range) - 2; in lpt_program_iclkip()
5669 if (divsel <= 0x7f) in lpt_program_iclkip()
5674 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) & in lpt_program_iclkip()
5681 clock, auxdiv, divsel, phasedir, phaseinc); in lpt_program_iclkip()
5688 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); in lpt_program_iclkip()
5716 u32 divsel, phaseinc, auxdiv; in lpt_get_iclkip() local
5734 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> in lpt_get_iclkip()
5745 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; in lpt_get_iclkip()
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