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Searched refs:dpll_mask (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/rcar-du/
Drcar_du_drv.c131 .dpll_mask = BIT(1),
160 .dpll_mask = BIT(1),
215 .dpll_mask = BIT(1),
363 .dpll_mask = BIT(2) | BIT(1),
392 .dpll_mask = BIT(1),
421 .dpll_mask = BIT(1),
Drcar_du_drv.h67 unsigned int dpll_mask; member
Drcar_du_crtc.c222 if (rcdu->info->dpll_mask & (1 << rcrtc->index)) { in rcar_du_crtc_set_display_timing()
1236 } else if (rcdu->info->dpll_mask & BIT(hwindex)) { in rcar_du_crtc_create()
/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c284 unsigned long dpll_mask) in intel_find_shared_dpll() argument
293 drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); in intel_find_shared_dpll()
295 for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { in intel_find_shared_dpll()
3518 unsigned long dpll_mask; in icl_get_combo_phy_dpll() local
3537 dpll_mask = in icl_get_combo_phy_dpll()
3542 dpll_mask = in icl_get_combo_phy_dpll()
3547 dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); in icl_get_combo_phy_dpll()
3551 dpll_mask &= ~intel_get_hti_plls(dev_priv); in icl_get_combo_phy_dpll()
3555 dpll_mask); in icl_get_combo_phy_dpll()