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Searched refs:dsiclk (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/bridge/
Dtc358768.c159 u32 dsiclk; /* pll_clk / 2 */ member
376 priv->dsiclk = best_pll / 2; in tc358768_calc_pll()
603 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); in tc358768_setup_pll()
605 tc358768_pll_to_pclk(priv, priv->dsiclk * 2), in tc358768_setup_pll()
645 u32 dsiclk, dsibclk; in tc358768_bridge_pre_enable() local
670 dsiclk = priv->dsiclk; in tc358768_bridge_pre_enable()
671 dsibclk = dsiclk / 4; in tc358768_bridge_pre_enable()
720 dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); in tc358768_bridge_pre_enable()
816 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, in tc358768_bridge_pre_enable()
Dtc358775.c381 u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay; in tc_bridge_enable() local
431 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000; in tc_bridge_enable()
432 clkdiv = dsiclk / DIVIDE_BY_3 * tc->lvds_link; in tc_bridge_enable()
433 byteclk = dsiclk / 4; in tc_bridge_enable()
/drivers/mfd/
Ddb8500-prcmu.c502 struct dsiclk { struct
508 static struct dsiclk dsiclk[2] = { variable
1349 val &= ~dsiclk[n].divsel_mask; in request_dsiclk()
1350 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << in request_dsiclk()
1351 dsiclk[n].divsel_shift); in request_dsiclk()
1508 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); in dsiclk_rate()
1511 divsel = dsiclk[n].divsel; in dsiclk_rate()
1513 dsiclk[n].divsel = divsel; in dsiclk_rate()
1882 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : in set_dsiclk_rate()
1887 val &= ~dsiclk[n].divsel_mask; in set_dsiclk_rate()
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